Patents by Inventor Meng-Kai Hsu

Meng-Kai Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250217563
    Abstract: A method including: providing a design data of an integrated circuit (IC), the design data including a first cell; identifying a first conductive line in the first cell as a critical internal net of the first cell, wherein the first conductive line is determined as being close to a cell boundary of the first cell; providing a library of the first cell, wherein the library includes a table of timing parameters or power parameters of the first cell associated with different configurations; updating the design data by determining a timing or power value of the first cell based on the table; performing a timing analysis on the updated design data; and forming a photomask based on the updated design data in response to determining that the timing analysis of the updated design data complies with a specification.
    Type: Application
    Filed: March 18, 2025
    Publication date: July 3, 2025
    Inventors: SHI-HAN ZHANG, YOU-CHENG LAI, JERRY CHANG JUI KAO, PEI-WEI LIAO, SHANG-CHIH HSIEH, MENG-KAI HSU, CHIH-WEI CHANG
  • Patent number: 12346645
    Abstract: A semiconductor device, method, and system of arranging patterns of the same are provided. The method includes generating a plurality of gate patterns and conductive patterns, wherein each of the plurality of gate patterns and conductive patterns is located at a first horizontal level and extends along a first direction. The method also includes selecting one of the gate patterns as an input pin or one of the conductive patterns as an output pin. The method further includes generating, based on a selected gate pattern or a selected conductive pattern, a plurality of metallization patterns. Each of the plurality of metallization patterns is located at a second horizontal level overlying the first horizontal level and extends along a second direction substantially perpendicular to the first direction.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: July 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Anurag Verma, Meng-Kai Hsu, Johnny Chiahao Li, Sheng-Hsiung Chen, Cheng-Yu Lin, Hui-Zhong Zhuang, Jerry Chang Jui Kao
  • Patent number: 12282723
    Abstract: A method including: providing a design data of an integrated circuit (IC), the design data comprising a first cell; identifying a first conductive line in the first cell as a critical internal net of the first cell, wherein the first conductive line is electrically connected between an input terminal of the first cell and an output terminal of the first cell; providing a library of the first cell, wherein the library includes a table of timing or power parameters of the first cell based on a multidimensional input set associated with the critical internal net; updating the design data by determining a timing or power value of the first cell based on the table; performing a timing analysis on the updated design data; and forming a photomask based on the updated design data.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: April 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shi-Han Zhang, You-Cheng Lai, Jerry Chang Jui Kao, Pei-Wei Liao, Shang-Chih Hsieh, Meng-Kai Hsu, Chih-Wei Chang
  • Patent number: 12277379
    Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: April 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang, Yi-Kan Cheng, Chi-Yu Lu, Jung-Chou Tsai
  • Patent number: 12216978
    Abstract: A layout method and a semiconductor device are disclosed. The layout method includes: generating a design layout by placing a cell, wherein the cell includes: a first conductive segment overlapping a source/drain region and disposed immediately adjacent to a first power rail, wherein the first conductive segment has a length substantially equal to a cell length; a second conductive segment; and a third conductive segment between the first and second conductive segments. The layout method further includes: providing a fourth conductive segment and a fifth conductive segment to the design layout, wherein the fourth and fifth conductive segments are aligned in a first direction.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Anurag Verma, Meng-Kai Hsu, Chih-Wei Chang, Sang-Chi Huang, Wei-Ling Chang, Hui-Zhong Zhuang
  • Patent number: 12216981
    Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang, Yi-Kan Cheng, Chi-Yu Lu, Jung-Chou Tsai
  • Patent number: 12164853
    Abstract: The present disclosure provides a method and an apparatus for generating a layout of a semiconductor device. The method includes placing a first cell and a second cell adjacent to the first cell, placing a first conductive pattern in a first track of the first cell extending in a first direction, wherein the first conductive pattern is configured as an input terminal or an output terminal of the first cell, placing a second conductive pattern in a first track of the second cell extending in the first direction, wherein the second conductive pattern is configured as an input terminal or an output terminal of the second cell, and aligning the first conductive pattern with the second conductive pattern.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Anurag Verma, Chi-Chun Liang, Meng-Kai Hsu, Cheng-Yu Lin, Pochun Wang, Hui-Zhong Zhuang
  • Publication number: 20240378365
    Abstract: A semiconductor cell structure includes: a gate electrode extending in a first direction over a substrate; a first and a second power rails extending in a second direction different from the first direction in a first layer over the substrate, wherein the first power rail and the second power rail are disposed on opposite sides of the cell structure; first conductive segments extending in the second direction between the first and second power rails in the first layer; a third power rail extending in the first direction in a second layer over the first layer; and second conductive segments extending in the first direction in the second layer. At least two of the second conductive segments are aligned with a single track line in the cell structure in the first direction and are separated by a spacing substantially equal to or greater than a minimal segment end spacing.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: ANURAG VERMA, MENG-KAI HSU, CHIH-WEI CHANG, SANG-CHI HUANG, WEI-LING CHANG, HUI-ZHONG ZHUANG
  • Patent number: 11943939
    Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Kai Hsu, Jerry Chang Jui Kao, Chin-Shen Lin, Ming-Tao Yu, Tzu-Ying Lin, Chung-Hsing Wang
  • Publication number: 20230403868
    Abstract: A method includes forming a circuit region over a substrate. The circuit region includes at least one active region extending along a first direction, and at least one gate region extending across the at least one active region and along a second direction transverse to the first direction. At least one first input/output (TO) pattern and at least one second TO pattern are correspondingly formed in different first and second metal layers to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first TO pattern extends along a third direction oblique to both the first direction and the second direction. The at least one second TO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 14, 2023
    Inventors: Jerry Chang Jui KAO, Meng-Kai HSU, Chin-Shen LIN, Ming-Tao YU, Tzu-Ying LIN, Chung-Hsing WANG
  • Publication number: 20230394219
    Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 7, 2023
    Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Hui-Zhong ZHUANG, Meng-Kai HSU, Pin-Dai SUE, Po-Hsiang HUANG, Yi-Kan CHENG, Chi-Yu LU, Jung-Chou TSAI
  • Publication number: 20230385522
    Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Hui-Zhong ZHUANG, Meng-Kai HSU, Pin-Dai SUE, Po-Hsiang HUANG, Yi-Kan CHENG, Chi-Yu LU, Jung-Chou TSAI
  • Patent number: 11829700
    Abstract: A method includes clustering cells in a group of cells into a selected number of clusters, and ranking the clusters based on a list of prioritized features to generate a list of ranked clusters. The method also includes ranking cells in each of one or more ranked clusters in the list of ranked clusters, based on the list of prioritized features, to generate a list of ranked critical cells. The method further includes outputting the list of ranked critical cells for use in adjusting cell layouts based on the ranked critical cells.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Anurag Verma, Meng-Kai Hsu, Chih-Wei Chang
  • Patent number: 11790151
    Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang, Yi-Kan Cheng, Chi-Yu Lu, Jung-Chou Tsai
  • Patent number: 11775727
    Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang, Yi-Kan Cheng, Chi-Yu Lu, Jung-Chou Tsai
  • Patent number: 11741286
    Abstract: A method (of generating a layout diagram) includes identifying, in the layout diagram, a group of three or more cells arranged so as to exhibit two or more edge-pairs (EPs) that are edge-wise abutted relative to a first direction. The method further includes, for each of at least one but fewer than all of the three or more cells, selectively moving a given one of cells corresponding to one of the members of the corresponding EP resulting in at least a minimum gap in the first direction between the members of the corresponding EP.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Kai Hsu, Sheng-Hsiung Chen, Wai-Kei Mak, Ting-Chi Wang, Yu-Hsiang Cheng, Ding-Wei Huang
  • Publication number: 20230259686
    Abstract: A semiconductor device, method, and system of arranging patterns of the same are provided. The method includes generating a plurality of gate patterns and conductive patterns, wherein each of the plurality of gate patterns and conductive patterns is located at a first horizontal level and extends along a first direction. The method also includes selecting one of the gate patterns as an input pin or one of the conductive patterns as an output pin. The method further includes generating, based on a selected gate pattern or a selected conductive pattern, a plurality of metallization patterns. Each of the plurality of metallization patterns is located at a second horizontal level overlying the first horizontal level and extends along a second direction substantially perpendicular to the first direction.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Inventors: ANURAG VERMA, MENG-KAI HSU, JOHNNY CHIAHAO LI, SHENG-HSIUNG CHEN, CHENG-YU LIN, HUI-ZHONG ZHUANG, JERRY CHANG JUI KAO
  • Publication number: 20230259680
    Abstract: A method including: providing a design data of an integrated circuit (IC), the design data comprising a first cell; identifying a first conductive line in the first cell as a critical internal net of the first cell, wherein the first conductive line is electrically connected between an input terminal of the first cell and an output terminal of the first cell; providing a library of the first cell, wherein the library includes a table of timing or power parameters of the first cell based on a multidimensional input set associated with the critical internal net; updating the design data by determining a timing or power value of the first cell based on the table; performing a timing analysis on the updated design data; and forming a photomask based on the updated design data.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: SHI-HAN ZHANG, YOU-CHENG LAI, JERRY CHANG JUI KAO, PEI-WEI LIAO, SHANG-CHIH HSIEH, MENG-KAI HSU, CHIH-WEI CHANG
  • Publication number: 20230237235
    Abstract: An integrated circuit includes a first circuit cell having a first width and a second circuit cell having a second width that is wider than the first width by at least one contacted poly pitch. An equivalent circuit of the first circuit cell is the same as an equivalent circuit of the second circuit cell.
    Type: Application
    Filed: June 15, 2022
    Publication date: July 27, 2023
    Inventors: Anurag VERMA, Meng-Kai HSU, ChiWei HU
  • Publication number: 20230222278
    Abstract: The present disclosure provides a method and an apparatus for generating a layout of a semiconductor device. The method includes placing a first cell and a second cell adjacent to the first cell, placing a first conductive pattern in a first track of the first cell extending in a first direction, wherein the first conductive pattern is configured as an input terminal or an output terminal of the first cell, placing a second conductive pattern in a first track of the second cell extending in the first direction, wherein the second conductive pattern is configured as an input terminal or an output terminal of the second cell, and aligning the first conductive pattern with the second conductive pattern.
    Type: Application
    Filed: January 12, 2022
    Publication date: July 13, 2023
    Inventors: ANURAG VERMA, CHI-CHUN LIANG, MENG-KAI HSU, CHENG-YU LIN, POCHUN WANG, HUI-ZHONG ZHUANG