Abstract: The present disclosure is directed to a method for triple-patterning friendly placement. The method can include creating cell attributes identifying potential risk for triple-patterning design rule checking (TP DRC) violations in both a vertical and a horizontal propagation in a placement region. Based on these cell attributes, placement blockages can be inserted to prevent TP DRC violations after cell placement.

Abstract: A method is disclosed that includes: if there is a conflict graph including a sub-graph representing that each spacing between any two of three adjacent patterns of quadruple-patterning (QP) patterns in at least one of two abutting cells is smaller than a threshold spacing, performing operations including: identifying if one of edges that connect the three adjacent patterns of QP patterns to one another is constructed along, and/or in parallel with, a boundary between the two abutting cells; modifying multiple-patterning patterns of a layout of an integrated circuit (IC) to exclude patterns representing the sub-graph; and initiating generation of the IC from the modified multiple-patterning patterns, wherein at least one operation of identifying , modifying, or initiating is performed by at least one processor.

Abstract: In some embodiments, in a method performed by at least one processor, spaces among a plurality of layout segments is analyzed by the at least one processor to determine at least one first-type conflicted edge according to a first predetermined length. Spaces among the plurality of layout segments is analyzed by the at least one processor to determine a plurality of potential conflicted edges according to a second predetermined length different from the first predetermined length. At least one second-type conflicted edge is determined by the at least one processor according to the plurality of potential conflicted edges. If at least one odd-vertex loop is formed in the plurality of layout segments is checked by the at least one processor according to the at least one first-type conflicted edge and the at least one second-type conflicted edge to determine if a violation occurs in the plurality of layout segments.

Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.

Abstract: A method for legalizing mixed-cell height standard cells of an IC is provided. A target standard cell is obtained in a window of a global placement. The target standard cell has a first area overlapping a first standard cell located in a first row of the window, and a second area overlapping a second standard cell located in a second row of the window. The target standard cell and the first standard cell are moved until the target standard cell does not overlap the first standard cell in the first row of the window. The target standard cell and the first standard cell are clustered as a first cluster when the target standard cell does not overlap the first standard cell. The first cluster is moved away from the second standard cell in the second row until the second standard cell does not overlap the first cluster.

Abstract: A method is disclosed that includes determining whether there is a conflict graph representing that each spacing between any two of at least five adjacent patterns of multiple-patterning patterns of a layout of an integrated circuit (IC) is less than a threshold spacing, and if there is the conflict graph, modifying the multiple-patterning patterns to exclude patterns represented by the conflict graph, for fabrication of the IC.

Abstract: A method is applied to reconfigure a set of uncrowned standard cells in a layout of a semiconductor apparatus. Each uncrowned standard cell includes a standard first array. Each standard first array includes a first stacked arrangement of vias interspersed with first segments of corresponding M(i)˜M(N) metallization layers. The M(N) metallization layer includes second segments which connect corresponding first segments of the M(N) metallization layer in the first standard arrays. The method includes crowning each first standard array in the set with a corresponding second standard array. Each standard second array includes a second stacked arrangement of vias interspersed with corresponding first segments of corresponding M(N+1)˜M(N+Q) metallization layers. The method further includes: adding, to the M(N+Q) layer, second segments which connect corresponding first segments of the M(N+Q) metallization layer in the corresponding second standard arrays.

Abstract: The present disclosure is directed to a method for triple-patterning friendly placement. The method can include creating cell attributes identifying potential risk for triple-patterning design rule checking (TP DRC) violations in both a vertical and a horizontal propagation in a placement region. Based on these cell attributes, placement blockages can be inserted to prevent TP DRC violations after cell placement.

Abstract: The present disclosure is directed to systems and methods for using multiple libraries with different cell pre-coloring. In embodiments, the present disclosure determines a first set of cells to be placed using a single library methodology for pre-coloring and a second set of cells to be placed using a multiple library methodology for pre-coloring. In further embodiments, color-aware cell swapping can be performed based on the first set of cells and the second set of cells to align cells to swap the pre-coloring arrangements of cells to align with a track color of a closest legalization site candidate.

Abstract: A method is disclosed that includes determining whether there is a conflict graph representing that each spacing between any two of at least five adjacent patterns of multiple-patterning patterns of a layout of an integrated circuit (IC) is less than a threshold spacing, and if there is the conflict graph, modifying the multiple-patterning patterns to exclude patterns represented by the conflict graph, for fabrication of the IC.

Abstract: In some embodiments, in a method performed by at least one processor, spaces among a plurality of layout segments is analyzed by the at least one processor to determine at least one first-type conflicted edge according to a first predetermined length. Spaces among the plurality of layout segments is analyzed by the at least one processor to determine a plurality of potential conflicted edges according to a second predetermined length different from the first predetermined length. At least one second-type conflicted edge is determined by the at least one processor according to the plurality of potential conflicted edges. If at least one odd-vertex loop is formed in the plurality of layout segments is checked by the at least one processor according to the at least one first-type conflicted edge and the at least one second-type conflicted edge to determine if a violation occurs in the plurality of layout segments.

Abstract: A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns.

Abstract: A method for design rule checking (DRC) during a static timing analysis (STA) of an integrated circuit (IC) design comprises analyzing cells with distorted waveforms in a cell library and generating both library-based waveforms and simulated waveforms for said each cell type according to a plurality of parameters for the cell type. The method further comprises constructing a lookup table based on analysis of the distorted waveforms, wherein the lookup table maps a waveform error to a hold time constraint error of each cell type in the library. The method further comprises identifying one or more cells in the IC design as risky for a timing constraint violation during the STA of the IC design according to the lookup table and re-optimizing the identified risky cell(s) is to reduce risk for the timing constraint violation of the IC design.

Abstract: A method of wire routing is provided. The method comprises obtaining data of cell layouts, generating a first database for the cell layouts, identifying, for each cell in the first database, whether the cell and another cell in the first database are routable in a pin layer, and generating a second database for routable cells.

Abstract: A method for design rule checking (DRC) during static timing analysis (STA) of an integrated circuit (IC) design comprises analyzing cells with distorted waveforms in a cell library and generating both library-based and simulated waveforms for each cell type according to a plurality of parameters for the cell type. The method further comprises constructing a lookup table based on analysis of the distorted waveforms, wherein the lookup table maps waveform error to hold time constraint error of each cell type in the library. The method further comprises identifying one or more cells in the IC design as risky for timing constraint violation during static timing analysis of the IC design according to the lookup table and re-optimizing the identified risky cells to reduce risk for timing violation of the IC design.

Abstract: A method of wire routing is provided. The method comprises obtaining data of cell layouts, generating a first database for the cell layouts, identifying, for each cell in the first database, whether the cell and another cell in the first database are routable in a pin layer, and generating a second database for routable cells.

Abstract: A method includes generating one or more routes usable for implementing a conductive path of an integrated circuit. A corresponding cost function value for the one or more routes is calculated according to a first cost function, including adjusting the corresponding cost function value based on whether the corresponding route is at least partially assigned to be formed in a conductive layer by a first patterning process or a second patterning process. The integrated circuit has electrical devices and the conductive layer, and the conductive layer has a first set of conductive lines formed by the first patterning process and a second set of conductive lines formed by the second patterning process. The first set of conductive lines has a unit resistance less than that of the second set of conductive lines. The conductive path electrically connects two of the electrical devices of the integrated circuit.

Abstract: A method includes generating one or more routes usable for implementing a conductive path of an integrated circuit. A corresponding cost function value for the one or more routes is calculated according to a first cost function, including adjusting the corresponding cost function value based on whether the corresponding route is at least partially assigned to be formed in a conductive layer by a first patterning process or a second patterning process. The integrated circuit has electrical devices and the conductive layer, and the conductive layer has a first set of conductive lines formed by the first patterning process and a second set of conductive lines formed by the second patterning process. The first set of conductive lines has a unit resistance less than that of the second set of conductive lines. The conductive path electrically connects two of the electrical devices of the integrated circuit.

Abstract: A computer-implemented method to generate a placement for a plurality of instances for an integrated circuit (IC) by utilizing a novel weighted-average (WA) wirelength model, which outperforms a well-known log-sum-exp wirelength model, to approximate the total wirelength. The placement is determined by performing an optimization process on an objective function which includes a wirelength function approximated by the WA wirelength model. The method can be extended to generate a placement for a plurality of instances for a three-dimensional (3D) integrated circuit (IC) which considers the sizes of through-silicon vias (TSVs) and the physical positions for TSV insertion. With the physical positions of TSVs determined during placement, 3D routing can easily be accomplished with better routed wirelength, TSV counts, and total silicon area.

Abstract: A computer-implemented method to generate a placement for a plurality of instances for an integrated circuit (IC) by utilizing a novel weighted-average (WA) wirelength model, which outperforms a well-known log-sum-exp wirelength model, to approximate the total wirelength. The placement is determined by performing an optimization process on an objective function which includes a wirelength function approximated by the WA wirelength model. The method can be extended to generate a placement for a plurality of instances for a three-dimensional (3D) integrated circuit (IC) which considers the sizes of through-silicon vias (TSVs) and the physical positions for TSV insertion. With the physical positions of TSVs determined during placement, 3D routing can easily be accomplished with better routed wirelength, TSV counts, and total silicon area.