Abstract: Embodiments of the invention relate to symmetric encryption that converts plain text to Diophantine equations, i.e. cipher text, and communication of the Diophantine equations by electromagnetic, mechanical and/or matter waves or signals. More particularly, at least one wave characteristic of electromagnetic, mechanical and/or matter waves or signals are utilised to define the Diophantine equations.

Abstract: A semiconductor package includes an interposer including a first redistribution structure, a first semiconductor die electrically coupled to the first redistribution structure through conductive joints, and a first encapsulant disposed on the first redistribution structure and laterally covering the first semiconductor die. The first semiconductor die includes a semiconductor substrate including a first side facing the first redistribution structure and a second side opposite to the first side, a through substrate via provided within the semiconductor substrate, and a passive device disposed between the second side of the semiconductor substrate and the conductive joints.

Abstract: A semiconductor package includes a chiplet, a first underfill surrounding the chiplet, and a first encapsulant laterally covering the first underfill. The chiplet includes a semiconductor substrate and die connectors disposed over the semiconductor substrate. The first underfill includes first fillers, and a portion of the first fillers has a substantially planar surface at a first surface of the first underfill. The first encapsulant includes a first surface and a second surface opposite to the first surface, the first surface is substantially leveled with surfaces of the die connectors, and the second surface is substantially leveled with the first surface of the first underfill.

Abstract: Embodiments of the invention provide a two-dimensional code which comprises a plurality of optically readable and distinct indicia which are arranged on a two-dimensional area, wherein the indicia include a reference indicium and further includes at least one data indicium which represents at least one data value respectively, wherein the at least one data value is represented by at least one distance between the reference indicium and the at least one data indicium, and at least one angular displacement of the at least one data indicium which is relative to a reference direction, and wherein the reference direction is based on at least one of the indicia which is asymmetric or includes at most one line of symmetry. FIG.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

Abstract: Semiconductor packages and methods of fabricating semiconductor packages include an interposer, at least one semiconductor integrated circuit (IC) die mounted on a first surface of the interposer, a package substrate bonded to a second surface of the interposer, and a molding portion contacting the second surface of the interposer and laterally surrounding the package substrate. The package substrate may be laterally-confined with respect to the interposer such that at least one horizontal dimension of the package substrate may be less than the corresponding horizontal dimension of the interposer. In various embodiments, reliability of the bonding connections between the interposer and the package substrate may be improved thereby providing increased yields and improved package performance.

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

Abstract: A semiconductor structure includes a circuit substrate, at least one semiconductor package, at least one semiconductor device, and a ring structure. The at least one semiconductor package is disposed on the circuit substrate, and the semiconductor package includes a plurality of integrated circuit structures. The at least one semiconductor device, disposed on the circuit substrate and aside the semiconductor package. The ring structure is disposed on the circuit board. The ring structure includes at least one opening pattern corresponding to the semiconductor device.

Abstract: A semiconductor device includes an interposer, a first die, a second die, a third die and a dummy die. The interposer includes a first region and a second region. The first die and the second die are bonded to a first surface of the interposer, the first die is disposed in the first region, and the second die is disposed in the second region. The third die and the dummy die are bonded to a second surface opposite to the first surface of the interposer, wherein the third die is disposed in the first region and the dummy die is disposed in the second region.

Abstract: A semiconductor package, which may correspond to a high-performance computing package, includes an integrated circuit die electrically and/or mechanically connected to a top surface of an interposer and a plurality of connection structures electrically and/or mechanically connected to a bottom surface of the interposer. The top surface of the interposer includes a set of test contact structures (e.g., one or more test bumps) that are electrically connected to the integrated circuit die through traces of the interposer. The set of test structures may be contacted by a probe needle to test a quality and/or a reliability of the integrated circuit die, as well as verify that traces of the interposer are functional. The set of test contact structures allows the integrated circuit die and traces of the interposer to be tested without probing the connection structures.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Abstract: A package structure includes a package substrate, a semiconductor die module on the package substrate, a first adhesive and a second adhesive on the package structure, wherein the second adhesive is between the first adhesive and the semiconductor die module, and a ring structure on the package substrate around the semiconductor die module, wherein the ring structure includes an outer ring attached to the package substrate by the first adhesive, and an inner ring between the semiconductor die module and the outer ring and attached to the package substrate by the second adhesive.

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

Abstract: A semiconductor device includes a bottom die including a first semiconductor layer, and a first redistribution layer (RDL) disposed on a bottom surface of the first semiconductor layer; a top die disposed on a top surface of the first semiconductor layer and including a second semiconductor layer, and a second RDL disposed on the top surface of the first semiconductor layer; a stress control (SC) layer disposed on the top surface of the first semiconductor layer and side surfaces of the first die; and a dielectric layer disposed on the SC layer, wherein the SC layer is configured to apply a compressive stress of at least ?100 MPa to the top surface of the first semiconductor layer, or the SC layer is configured to apply a tensile stress of at least 100 MPa to the top surface of the first semiconductor layer.

Abstract: A semiconductor package, which may correspond to a high-performance computing package, includes an integrated circuit die electrically and/or mechanically connected to a top surface of an interposer and a plurality of connection structures electrically and/or mechanically connected to a bottom surface of the interposer. The top surface of the interposer includes a set of test contact structures (e.g., one or more test bumps) that are electrically connected to the integrated circuit die through traces of the interposer. The set of test structures may be contacted by a probe needle to test a quality and/or a reliability of the integrated circuit die, as well as verify that traces of the interposer are functional. The set of test contact structures allows the integrated circuit die and traces of the interposer to be tested without probing the connection structures.

Abstract: The present disclosure provides a method for displaying mark information performed by a computer device. The method includes: determining that a first virtual object controlled by a user of the computer device participates in a game task; displaying a preparation interface before the first virtual object enters a virtual game scene configured for the game task; after a target scene point in the virtual game is marked, displaying entry prompt information matching the target scene point in the preparation interface; and in response to an operation performed on an invitation control matching the target scene point, transmitting first entry invitation information to a second virtual object participating in the game task, the first entry invitation information including the target scene point for the second virtual object to follow the first virtual object in the game task.

Abstract: Vertically stacked semiconductor devices and methods of fabrication thereof that include a first semiconductor die bonded to a second device structure in a face-down configuration, a gap fill dielectric layer laterally surrounding the first semiconductor die, and a recess fill dielectric layer formed over the gap fill dielectric layer to fill concave recess defects in the gap fill dielectric that may result from cracks in the first semiconductor die. The recess fill dielectric layer may fill the entire volume of one or more concave recess defects in the gap fill dielectric material to a vertical depth of 5 ?m or more below the backside surface of a semiconductor substrate of the first semiconductor die. Providing a recess fill dielectric layer within concave recess defects in the gap fill dielectric layer may result in enhanced protection against electrical arcing during subsequent processing steps and thereby provide improved device yields.

Abstract: The invention introduces a system for acquiring data on poultry body size, utilizing a baseplate for immobilization. After positioning the poultry, the system adjusts a fixing device on a rod to secure the poultry's knee joints using a fixing clip, thereby stabilizing the poultry's body. A 3D laser scanning lens then conducts comprehensive 3D scanning of the poultry's entire body, transmitting the data to a 3D microcomputer which generates an optimal dynamic model image. This microcomputer organizes and analyzes data from the model using a computer algorithm, ultimately displaying the poultry's body size indices on the 3D microcomputer's display. This method circumvents inaccuracies common with traditional tools like electronic scales, enhancing the speed and precision of poultry body composition data collection.

Abstract: A method forming a redistribution line, which includes a via and a metal trace over and joined to the via, over a carrier. The formation of the redistribution line includes depositing a first metal layer, depositing a barrier layer over the first metal layer, and depositing a second metal layer over the barrier layer. The method further includes de-bonding the redistribution line from the carrier, and bonding a package component to the redistribution line, wherein a metal bump bonds the package component to the via.