Abstract: A single-chip integrated circuit is disclosed, wherein the single-chip integrated circuit comprises at least one unidirectional communication channel for converting a first electrical signal to a first optical signal and at least one bidirectional communication channel for converting a second electrical signal to a second optical signal and converting a third optical signal to a third electrical signal.

Abstract: An equalizer system includes at least one equalizer configured to equalize an input signal to generate an equalized input signal; a limiting amplifier coupled to the at least one equalizer, and configured to amplify the equalized input signal to a saturated level to generate an output signal; and a control circuit coupled to the at least one equalizer and the limiting amplifier, and configured to generate at least one control signal to the at least one equalizer according to the equalized input signal to adjust a peak gain of the at least one equalizer, wherein the peak gain of the at least one equalizer is at a Nyquist frequency.

Abstract: A universal tuning module may include an oscillator, a first tuner configured to process a first television signal, a second tuner configured to process a second television signal, a first switch configured to pass its input containing information associated with an output of the oscillator to said first tuner, and a second switch configured to pass its input containing information associated with the output of the oscillator to the second tuner.

Abstract: An automatic gain control circuit for controlling an LNA for inputting signals carrying packets, the automatic gain control circuit can perform a background calibration in the non-preamble time region of a first packet for pre-determining a gain adjustment to the LNA before the next preamble of a second packet arrives, so that the gain of the LNA can be adjusted immediately according to the pre-determined gain adjustment when the next preamble of the second packet arrives.

Abstract: The present invention discloses a laser power control system includes a laser diode, a monitor photodiode, a bias control circuit, a modulation control circuit, a digital controller, and a laser diode driver. The laser power control system forms an automatic extinction ratio control loop that is configured to control the extinction ratio of the laser diode by comparing a monitor current with a first target current to keep the extinction ratio of the laser diode at the predetermined first target current. The laser power control system forms an automatic power control loop that is configured to control the average power of the laser diode by comparing the monitor current with the second target current to keep the average power of the laser diode at the predetermined second target current.

Abstract: An automatic gain control circuit for controlling an LNA for inputting signals carrying packets, the automatic gain control circuit can perform a background calibration in the non-preamble time region of a first packet for pre-determining a gain adjustment to the LNA before the next preamble of a second packet arrives, so that the gain of the LNA can be adjusted immediately according to the pre-determined gain adjustment when the next preamble of the second packet arrives.

Abstract: An integrated multi-user satellite receiver includes: a single-chip, and the single-chip includes: a first synthesizer for generating a first oscillating signal having a first frequency; a first frequency multiplier for generating a second oscillating signal having a second frequency according to the first oscillating signal; a second synthesizer for generating a third oscillating signal having a third frequency; and a second frequency multiplier for generating a fourth oscillating signal having a fourth frequency according to the third oscillating signal; wherein the single-chip generates a first down-converted signal according to a first satellite signal and the second oscillating signal, generates a second down-converted signal according to the first satellite signal and the fourth oscillating signal, generates a third down-converted signal according to a second satellite signal and the second oscillating signal, and generates a fourth down-converted signal according to the second satellite signal and the

Abstract: An integrated circuit chip includes a first single-ended-to-differential amplifier configured to generate a differential output associated with an input of said first single-ended-to-differential amplifier; a second single-ended-to-differential amplifier arranged in parallel with said first single-ended-to-differential amplifier; a first set of switch circuits arranged downstream of said first single-ended-to-differential amplifier; a second set of switch circuits arranged downstream of said second single-ended-to-differential amplifier; and a first differential-to-single-ended amplifier arranged downstream of a first one of said switch circuits in said first set and downstream of a first one of said switch circuits in said second set.

Abstract: A signal receiver includes a first mixer configured to mix its first input with its second input associated with an oscillating output of a first synthesizer into an output; a first splitter configured to split its input associated with the output of the first mixer into a first output and a second output; a first switch matrix configured to switch its first input associated with the first output of the first splitter into a first output; a second switch matrix configured to switch its first input associated with the second output of the first splitter into a first output; a second mixer configured to mix its first input associated with the first output of the first switch matrix with its second input associated with an oscillating output of a second synthesizer into an output; and a third mixer configured to mix its first input associated with the first output of the second switch matrix with its second input associated with an oscillating output of a third synthesizer into an output.

Abstract: An integrated multi-user satellite receiver includes: a single-chip, and the single-chip includes: a first synthesizer for generating a first oscillating signal having a first frequency; a first frequency multiplier for generating a second oscillating signal having a second frequency according to the first oscillating signal; a second synthesizer for generating a third oscillating signal having a third frequency; and a second frequency multiplier for generating a fourth oscillating signal having a fourth frequency according to the third oscillating signal; wherein the single-chip generates a first down-converted signal according to a first satellite signal and the second oscillating signal, generates a second down-converted signal according to the first satellite signal and the fourth oscillating signal, generates a third down-converted signal according to a second satellite signal and the second oscillating signal, and generates a fourth down-converted signal according to the second satellite signal and the

Abstract: An integrated multi-user satellite receiver includes: a single-chip, and the single-chip includes: a first synthesizer for generating a first oscillating signal having a first frequency; a first frequency multiplier for generating a second oscillating signal having a second frequency according to the first oscillating signal; a second synthesizer for generating a third oscillating signal having a third frequency; and a second frequency multiplier for generating a fourth oscillating signal having a fourth frequency according to the third oscillating signal; wherein the single-chip generates a first down-converted signal according to a first satellite signal and the second oscillating signal, generates a second down-converted signal according to the first satellite signal and the fourth oscillating signal, generates a third down-converted signal according to a second satellite signal and the second oscillating signal, and generates a fourth down-converted signal according to the second satellite signal and the

Abstract: A channel receiving apparatus includes: a first modulating device converts a first channel into a first predetermined frequency according to a first oscillating signal and a second oscillating signal; and a second modulating device converts a second channel into a second predetermined frequency according to a third oscillating signal and a fourth oscillating signal; wherein the first oscillating signal has a first frequency, the second oscillating signal has a second frequency, the third oscillating signal has a third frequency, and the fourth oscillating signal has a fourth frequency, when the third frequency is substantially equal to the first frequency, the third oscillating signal is arranged to be shifted by a predetermined frequency range to have a fifth frequency different from the first frequency, and when the second frequency is substantially equal to the first frequency, the second frequency and the first frequency are shifted by the predetermined frequency range.

Abstract: An integrated circuit chip includes a first single-ended-to-differential amplifier configured to generate a differential output associated with an input of said first single-ended-to-differential amplifier; a second single-ended-to-differential amplifier arranged in parallel with said first single-ended-to-differential amplifier; a first set of switch circuits arranged downstream of said first single-ended-to-differential amplifier; a second set of switch circuits arranged downstream of said second single-ended-to-differential amplifier; and a first differential-to-single-ended amplifier arranged downstream of a first one of said switch circuits in said first set and downstream of a first one of said switch circuits in said second set.

Abstract: A channel receiving apparatus includes: a first modulating device converts a first channel into a first predetermined frequency according to a first oscillating signal and a second oscillating signal; and a second modulating device converts a second channel into a second predetermined frequency according to a third oscillating signal and a fourth oscillating signal; wherein the first oscillating signal has a first frequency, the second oscillating signal has a second frequency, the third oscillating signal has a third frequency, and the fourth oscillating signal has a fourth frequency, when the third frequency is substantially equal to the first frequency, the third oscillating signal is arranged to be shifted by a predetermined frequency range to have a fifth frequency different from the first frequency, and when the second frequency is substantially equal to the first frequency, the second frequency and the first frequency are shifted by the predetermined frequency range.

Abstract: An integrated circuit chip includes a first single-ended-to-differential amplifier configured to generate a differential output associated with an input of said first single-ended-to-differential amplifier; a second single-ended-to-differential amplifier arranged in parallel with said first single-ended-to-differential amplifier; a first set of switch circuits arranged downstream of said first single-ended-to-differential amplifier; a second set of switch circuits arranged downstream of said second single-ended-to-differential amplifier; and a first differential-to-single-ended amplifier arranged downstream of a first one of said switch circuits in said first set and downstream of a first one of said switch circuits in said second set.

Abstract: An integrated multi-user satellite receiver includes: a single-chip, and the single-chip includes: a first synthesizer for generating a first oscillating signal having a first frequency; a first frequency multiplier for generating a second oscillating signal having a second frequency according to the first oscillating signal; a second synthesizer for generating a third oscillating signal having a third frequency; and a second frequency multiplier for generating a fourth oscillating signal having a fourth frequency according to the third oscillating signal; wherein the single-chip generates a first down-converted signal according to a first satellite signal and the second oscillating signal, generates a second down-converted signal according to the first satellite signal and the fourth oscillating signal, generates a third down-converted signal according to a second satellite signal and the second oscillating signal, and generates a fourth down-converted signal according to the second satellite signal and the

Abstract: An integrated circuit chip includes a first single-ended-to-differential amplifier configured to generate a differential output associated with an input of said first single-ended-to-differential amplifier; a second single-ended-to-differential amplifier arranged in parallel with said first single-ended-to-differential amplifier; a first set of switch circuits arranged downstream of said first single-ended-to-differential amplifier; a second set of switch circuits arranged downstream of said second single-ended-to-differential amplifier; and a first differential-to-single-ended amplifier arranged downstream of a first one of said switch circuits in said first set and downstream of a first one of said switch circuits in said second set.

Abstract: A universal tuning module may include an oscillator, a first tuner configured to process a first television signal, a second tuner configured to process a second television signal, a first switch configured to pass its input containing information associated with an output of the oscillator to said first tuner, and a second switch configured to pass its input containing information associated with the output of the oscillator to the second tuner.

Abstract: A signal amplifying circuit includes: a first transistor having a first connecting terminal coupled to an input signal, and a controlling terminal coupled to a first reference voltage; an adjustable resistive circuit having a first terminal coupled to a second connecting terminal of the first transistor; and a second transistor having a first connecting terminal coupled to a second terminal of the adjustable resistive circuit, a controlling terminal coupled to a second reference voltage, and a second connecting terminal for outputting an output signal corresponding to the input signal; wherein a resistance of the adjustable resistive circuit is adjusted to make an input impedance looking into the first transistor from the first connecting terminal equal a predetermined impedance.

Abstract: A signal amplifying circuit includes: a first transistor having a first connecting terminal coupled to an input signal, and a controlling terminal coupled to a first reference voltage; an adjustable resistive circuit having a first terminal coupled to a second connecting terminal of the first transistor; and a second transistor having a first connecting terminal coupled to a second terminal of the adjustable resistive circuit, a controlling terminal coupled to a second reference voltage, and a second connecting terminal for outputting an output signal corresponding to the input signal; wherein a resistance of the adjustable resistive circuit is adjusted to make an input impedance looking into the first transistor from the first connecting terminal equal a predetermined impedance.