Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: A memory cell is disclosed. The memory cell includes a first transistor. The first transistor includes a first conduction channel collectively constituted by one or more first nanostructures spaced apart from one another along a vertical direction. The memory cell includes a second transistor electrically coupled to the first transistor in series. The second transistor includes a second conduction channel collectively constituted by one or more second nanostructures spaced apart from one another along the vertical direction. At least one of the one or more first nanostructures is applied with first stress by a first metal structure extending, along the vertical direction, into a first drain/source region of the first transistor.

Abstract: A memory device including a substrate, a sense amplifier that includes first gate-all-around transistors that have first drain/source regions that extend into the substrate, and bit cells that include fuse memory elements and second gate-all-around transistors. Each of the bit cells includes a fuse memory element having a first terminal connected to an input of the sense amplifier and a second terminal connected to a second gate-all-around transistor that includes second drain/source regions and a bottom dielectric isolation layer under the second drain/source regions.

Abstract: A semiconductor device includes a memory cell including a first transistor, a second transistor, and a resistor. Each of the first transistor and the second transistor is operatively coupled to the resistor in series. The second transistor is formed below the resistor such that the second transistor provides heat to the resistor when the memory cell is being programmed.

Abstract: A memory device includes an array having a plurality of one-time-programmable (OTP) memory cells formed over a side of a substrate, a plurality of word lines (WLs), a plurality of bit lines (BLs), and a plurality of control gate (CG) lines. Each of the OTP memory cells includes a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first and the second fuse resistors are connected to a corresponding one of the BLs, while the first and the second transistors are respectively gated by a first one and a second one of the CG lines. The first transistor, the second transistor, the first fuse resistor, and the second fuse resistor are respectively formed in a first one, a second one, a third one, and a fourth one of a plurality of metallization layers disposed on the side of the substrate.

Abstract: A memory device includes an anti-fuse memory cell that randomly presents either a first logic state or a second logic state. The memory cell is formed on a frontside of a substrate and at least includes a first programming transistor that is formed in a first one of a plurality of metallization layers disposed over the frontside and gated by a first programming word line, and a first reading transistor that is formed in a second one of the plurality of metallization layers disposed over the frontside or along a major surface on the frontside, coupled to the first programming transistor and a first bit line in series, and gated by a first reading word line.

Abstract: A memory device includes a plurality of memory cells, each of which includes a first transistor, a second transistor, and a resistor operatively coupled to each other in series. Each of the first and second transistors include a sub-transistor, the sub-transistor having a channel structure, a source structure disposed on one side of the channel structure, and a drain structure disposed on the other side of the channel structure. The resistor includes a metal structure disposed above the first and second transistors. The channel structures, source structures, and drain structures of the sub-transistors are all formed in a first active region of a substrate.

Abstract: A memory circuit may comprise a memory array comprising a plurality of memory cells, an input/output (I/O) circuit, and a power management circuit. The I/O circuit can be operatively coupled to the memory array and configured to read or write each of the memory cells. The power management circuit can be operatively coupled to the memory array and the I/O circuit. The power management circuit can be configured to provide a first gate control signal and a second gate control signal based on a received first supply voltage and a received second supply voltage. The first supply voltage can be substantially higher than two times the second supply voltage.

Abstract: A method includes forming a first gate structure across a first active region on a substrate within a memory region, wherein the first gate structure is of a first transistor being of a first conductivity type; forming a second gate structure across a second active region on the substrate within a peripheral region, wherein the second gate structure is of a second transistor being of a second conductivity type, the second conductivity type is opposite to the first conductivity type; forming a first gate contact over the first gate structure, the first gate contact overlapping with the first active region; forming a second gate contact over the second gate structure, the second gate contact non-overlapping with the second active region.

Abstract: A memory device is disclosed. The memory device includes a plurality of memory cells, each of the memory cells including an access transistor and a resistor coupled to each other in series. The resistors of the memory cells are each formed as one of a plurality of interconnect structures disposed over a substrate. The access transistors of the memory cells are disposed opposite a first metallization layer containing the plurality of interconnect structures from the substrate.

Abstract: A metal fuse structure may be provided. The metal fuse structure may comprise a first fuse element and a second fuse element. The second fuse element may be adjacent to the first fuse element for a length L. The second fuse element may be spaced apart from first fuse element by a width W.

Abstract: A method includes: coupling a first gate to a first word line through a first gate via, wherein the first gate extends along a first direction; coupling the first gate to a second word line through a second gate via, wherein each of the first gate, a second gate, the first gate via and the second gate via is disposed on a first active area which extends along the second direction, wherein the second gate extends along the first direction and is separated from the first gate along a second direction; coupling the first active area to a first bit line through a first conductive via; and aligning the first gate via, the second gate via and the a first conductive via with each other along the second direction.

Abstract: In the present disclosure, a semiconductor structure includes an Mx-1 layer including a first dielectric layer and first metal features, wherein the first metal features include a first set of first metal features in a first region and a second set of first metal features in a second region, wherein the first set has a first pattern density and the second set has a second pattern density being greater than the first pattern density. The structure further includes a Vx layer disposed over the Mx-1 layer, the Vx layer including first vias contacting the first set of the first metal features. The structure further includes an Mx layer disposed over the Vx layer, the Mx layer including a fuse element, wherein the fuse element has a first thickness in the first region less than a second thickness in the second region.

Abstract: A memory device includes peripheral transistors formed along a first surface of a substate; memory cells formed in one or more of first metallization layers disposed over the first surface, each of the memory cells being operatively coupled to a subset of the peripheral transistors and including a programming transistor and at least a first reading transistor; and second metallization layers disposed over a second surface of the substrate opposite to the first surface. A first source/drain terminal of the first reading transistor is in electrical connection with a first source/drain terminal of the programming transistor. A second source/drain terminal of the first reading transistor is in electrical connection with a bit line that is formed in a corresponding one of the second metallization layers.

Abstract: A memory device includes a transistor formed along a frontside surface of a substrate. The memory device includes a first fuse resistor formed in a first metallization layer that is vertically disposed with respect to the frontside surface. The memory device includes a second fuse resistor formed in a second metallization layer that is vertically disposed with respect to the frontside surface, the first metallization layer being different from the second metallization layer. The second fuse resistor and the first fuse resistor are each coupled to the transistor.

Abstract: A semiconductor device includes a first switch, a second switch, a third switch, and a fourth switch formed on a first side of a substrate, wherein the first switch and the second switch are connected in series between a first reference voltage and an output voltage, and wherein the third switch and the fourth switch are connected in series between the first reference voltage and a second reference voltage. The semiconductor device includes a capacitor formed on a second side of the substrate opposite to the first side, and having a first terminal and a second terminal. The first terminal is coupled to a first node between the first and second switches, and the second terminal is coupled to a second node between the third and fourth switches.

Abstract: A device includes a memory cell including a first transistor and a second transistor disposed on a frontside of a substrate, the substrate having a first area and a second area. The memory device includes a first interconnect structure disposed on a backside of the substrate. One S/D terminal of the first transistor is coupled to one S/D terminal of the second transistor, with the other S/D terminal of the second transistor coupled to the first interconnect structure through a first via structure in the first area. The memory device includes second via structures and a third via structure both disposed in the second area and each coupled to the first interconnect structure. The first via structure and the second via structures each have a cross-sectional area that is different from that of the third via structure.

Abstract: A memory device is disclosed. The memory device includes a memory array comprising a plurality of memory cells. At least a first one of the memory cells, by default, permanently presents a first logic state based on a short circuit. At least a second one of the memory cells, by default, permanently presents a second logic state opposite to the first logic state based on an open circuit.

Abstract: A memory device includes a memory cell having a transistor and a resistor coupled to each other, where the memory cell is on the first side, and the transistor further includes a plurality of first sub-transistors disposed in a first region of the substate. The memory device includes a plurality of second sub-transistors disposed in a second region of the substrate. The memory device further includes a first interconnect structure disposed on the second side. The first sub-transistors are each coupled to the first interconnect structure through a plurality of first via structures. The second sub-transistors are each coupled to the first interconnect structure through a plurality of second via structures and at least a third via structure, where the first via structures and the second via structures each have a first cross-sectional area, and the third via structure has a second cross-sectional area that is different from the first cross-sectional area.

Abstract: A semiconductor device includes a memory cell randomly presenting a first logic state or a second logic state and formed on a first side of a substrate, and a first and a second bit lines formed on a second side of the substrate opposite to the first side. The memory cell includes: a programming transistor having a first and a second source/drain terminals; a first reading transistor having a first source/drain terminal coupled to the first source/drain terminal of the programming transistor; and a second reading transistor having a first source/drain terminal coupled to the second source/drain terminal of the programming transistor. The first bit line is operatively coupled to a second source/drain terminal of the first reading transistor, and the second bit line is operatively coupled to a second source/drain terminal of the second reading transistor.