Abstract: A layout method includes: forming a layout structure of a memory array having first and second rows, each including a plurality of storage cells, wherein at least one of the storage cells includes a fuse; disposing a word line between the first and second rows; disposing a plurality of control electrodes across the word line for connecting the storage cells of the first row and the storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.

Abstract: An IC structure includes a bit line extending in a first direction, first and second pluralities of FinFETs, and a plurality of eFuses. The FinFETs of the first plurality of FinFETs alternate with the FinFETs of the second plurality of FinFETs along the bit line, each eFuse of the plurality of eFuses includes a conductive segment extending between first and second contact regions, the first contact region is electrically connected to the bit line, and the second contact region is electrically connected to each of an adjacent FinFET of the first plurality of FinFETs and an adjacent FinFET of the second plurality of FinFETs.

Abstract: A semiconductor device includes a component having a functionality. The semiconductor device further includes an interconnect structure electrically connected to the component. The interconnect structure is configured to electrically connect the component to a signal. The interconnect structure includes a first column of conductive elements and a second column of conductive elements. The interconnect structure further includes a first fuse on a first conductive level a first distance from the component, wherein the first fuse electrically connects the first column of conductive elements to the second column of conductive elements. The interconnect structure further includes a second fuse on a second conductive level a second distance from the component, wherein the second fuse electrically connects the first column of conductive elements to the second column of conductive elements, and the second distance is different from the first distance.

Abstract: A structure includes a first data line and a first anti-fuse cell including first/second programming devices and first/second reading devices. The first programming device includes a first gate and first/second source/drain regions disposing on opposite sides of first gate. The second programming device includes a second gate separate from the first gate and coupled to a first word line and third/fourth source/drain regions disposing on opposite sides of second gate. The first reading device includes a third gate and fifth/sixth source/drain regions disposing on opposite sides of third gate. The second reading device includes a fourth gate and seventh/eighth source/drain regions disposing on opposite sides of fourth gate. The third/fourth gates are parts of the first continuous gate coupled to a second word line. The fifth/seventh source/drain regions are coupled to the second/fourth source/drain regions, respectively. The sixth/eighth source/drain regions are coupled to the first data line.

Abstract: An integrated circuit is disclosed. The integrated circuit includes a transistor, a first fuse element and a second fuse element. The transistor is formed in a first conductive layer. The first fuse element is formed in a second conductive layer disposed above the first conductive layer. The second fuse element is formed in the second conductive layer and is coupled to the first fuse element. The transistor is coupled through the first fuse element to a first data line for receiving a first data signal, and the transistor is coupled through the second fuse element to a second data line for receiving a second data signal. A method of fabricating an integrated circuit (IC) is also disclosed herein.

Abstract: A layout method includes: forming a layout structure of a memory array having a first row, wherein the first row comprises a plurality of storage cells; disposing a word line; disposing a plurality of control electrodes for connecting the plurality of storage cells of the first row to the word line; and disposing a first cut layer on a first portion of a first control electrode of the plurality of control electrodes.

Abstract: A memory device includes at least one bit line, at least one source line, at least one program word line, at least one read word line, and at least one memory cell including a program transistor and a read transistor. The program transistor includes a gate terminal coupled to the at least one program word line, a first terminal coupled to the at least one source line, and a second terminal. The read transistor includes a gate terminal coupled to at least one read word line, a first terminal coupled to the at least one bit line, and a second terminal coupled to the second terminal of the program transistor.

Abstract: An IC structure includes a first FinFET including a first plurality of gate structures overlying a first plurality of fin structures, a second FinFET including a second plurality of gate structures overlying a second plurality of fin structures, and an eFuse including a conductive element positioned between the first and second pluralities of gate structures. The conductive element of the eFuse includes a first contact region electrically connected to each of the first and second pluralities of fin structures.

Abstract: A one time programmable memory device includes a field effect transistor and an antifuse structure. A first node of the antifuse structure includes, or is electrically connected to, the drain region of the field effect transistor. The antifuse structure includes an antifuse dielectric layer and a second node on, or over, the antifuse dielectric layer. One of the first node and the second node includes the drain region or a metal via structure formed within a via cavity extending through an interlayer dielectric material layer that overlies the field effect transistor.

Abstract: A memory device includes a programming gate-strip, a read gate-strip, and an array of one-bit memory cells. Each one-bit memory cell includes an anti-fuse structure, a transistor, a terminal conductor, a group of programming conducting lines, and a bit connector. The anti-fuse structure has a dielectric layer overlying a semiconductor region in an active zone at an intersection of the programming gate-strip and the active zone. The transistor has a channel region in the active zone at an intersection of the read gate-strip and the active zone. The terminal conductor overlies a terminal region of the transistor in the active zone. The group of programming conducting lines is conductively connected to the programming gate-strip through a group of one or more gate via-connectors. The bit connector is conductively connected to the terminal conductor through one or more terminal via-connectors.

Abstract: A memory device includes at least one bit line, at least one word line, and at least one memory cell comprising a capacitor and a transistor. The transistor has a gate terminal coupled to the word line, a first terminal, and a second terminal. The capacitor has a first end coupled to the first terminal of the transistor, a second end coupled to the bit line, and an insulating material between the first end and the second end. The insulating material is configured to break down under a predetermined break-down voltage or higher applied between the first end and the second end.

Abstract: A memory circuit includes a first programming device, a first circuit branch and a second circuit branch. The first programming device includes a first control terminal coupled to a first word line, and a first connecting end. The first circuit branch includes a first diode, and a first fuse element coupled to the first diode. The second circuit branch includes a second diode, and a second fuse element coupled to the second diode. The first circuit branch and the second circuit branch are coupled to the first connecting end of the first programming device.

Abstract: A memory device includes first nanostructures stacked on top of one another; first gate stacks, where two adjacent ones of the first gate stacks wrap around a corresponding first nanostructure; second nanostructures stacked on top of one another; second gate stacks, where two adjacent ones of the second gate stacks wrap around a corresponding second nanostructure; a first drain/source feature electrically coupled to a first end of the first nanostructures; a second drain/source feature electrically coupled to both of a second end of the first nanostructures and a first end of the second nanostructures; and a third drain/source feature electrically coupled to a second end of the second nanostructures. At least one of the plurality of first gate stacks is in direct contact with at least one of the first drain/source feature or the second drain/source feature.

Abstract: A memory circuit array includes a first read device and a first program device. The first read device is coupled to a first bit line. The first read device includes a first transistor coupled to a first word line, and a second transistor coupled to the first word line. The first program device is coupled to the first read device. The first program device includes a third transistor coupled to a second word line, and a fourth transistor coupled to the second word line.

Abstract: A method of forming a storage cell includes: forming a transistor on a semiconductor substrate; forming a plurality of fuses in at least one conductive layer on the semiconductor substrate to couple a connecting terminal of the transistor; forming a bit line to couple the plurality of fuses; and forming a word line to couple a control terminal of the transistor.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: A memory cell includes: a first transistor, having a first diffusion region coupled to a bit line and a first gate electrode coupled to a first word line; a second transistor, having a second diffusion region coupled to the bit line and a second gate electrode coupled to a second word line; and a third transistor, having a third diffusion region coupled to a fourth diffusion region of the first transistor, a fifth diffusion region coupled to a sixth diffusion region of the second transistor, and a third gate electrode coupled to a third word line; wherein the first transistor is arranged to have a first threshold voltage, the second transistor is arranged to have a second threshold voltage, and the second threshold voltage is different from the first threshold voltage.

Abstract: A method of manufacturing an anti-fuse device includes forming an anti-fuse structure on a substrate, forming a first transistor at a first position away from the anti-fuse device in a first direction, and forming a second transistor at a second position away from the anti-fuse device in a second direction opposite the first direction. Forming the anti-fuse structure includes forming first and second S/D structures in an active area, the first transistor includes the first S/D structure, and the second transistor includes the second S/D structure. The method includes constructing a first electrical connection between gate structures of the first and second transistors and a second electrical connection between a third S/D structure of the first transistor and a fourth S/D structure of the second transistor.

Abstract: A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, and a first gate electrode and a second gate electrode over the substrate and extending in a second direction. The semiconductor fin extends through the second gate electrode and terminates on the first gate electrode at one end. The memory device further includes a first conductive via over and electrically coupled to the first gate electrode. The one end of the semiconductor fin is surrounded by the first gate electrode.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.