Patents by Inventor Meng-Tse Chen

Meng-Tse Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9666572
    Abstract: A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Ming-Da Cheng, Meng-Tse Chen, Wen-Hsiung Lu, Kuei-Wei Huang, Chung-Shi Liu
  • Patent number: 9627355
    Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component coupled to a second package component by a first set of conductive elements. A first polymer-comprising material is arranged between the first package component and the second package component. The first polymer-comprising material surrounds the first set of conductive elements and the second package component. A third package component is coupled to the second package component by a second set of conductive elements. An underfill is arranged on the second package component and surrounds the second set of conductive elements. The first polymer-comprising material extends past sidewalls of the underfill.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9627369
    Abstract: A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chun-Cheng Lin, Yu-Peng Tsai, Hsiu-Jen Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9576888
    Abstract: A device comprises a bottom package comprising a plurality of metal bumps formed on a first side of the bottom package and a plurality of first bumps formed on a second side of the bottom package, a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps, and wherein second bumps and respective metal bumps form a joint structure and an underfill layer formed between the top package and the bottom package, wherein the metal bumps are embedded in the underfill layer.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chun-Cheng Lin, Wei-Yu Chen, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20170005074
    Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
  • Publication number: 20160380830
    Abstract: The disclosure is related to a method and a system for managing multiple devices within a network system. For the purpose of configuration or firmware synchronization for the devices within a network segment, the system allows an operator to optionally select the nodes operating as different roles such as a master, synchronization-source device, and slave. A selected device being the master is embedded with a web-based management mechanism, and therefore is remotely accessible. The management program provides a management interface in response to a management link. The management interface allows the operator to instruct the master to synchronize its configuration/firmware with the other selected nodes. Alternatively, through the master, one of the nodes is selected to be the synchronization-source device, and instructed to share its configuration to the other nodes. Through this management mechanism, the multiple nodes can be synchronized as applying the configuration, or/and firmware simultaneously.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Inventors: WEI JEN CHENG, MENG TSE CHEN
  • Patent number: 9508703
    Abstract: Semiconductor dies are bonded to each other and electrically connected to each other. An encapsulant is utilized to protect the semiconductor dies and external connections are formed to connect the semiconductor dies within the encapsulant. In an embodiment the external connections may comprise conductive pillars, conductive reflowable material, or combinations of such.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Sung-Feng Yeh, Meng-Tse Chen, Hui-Min Huang, Hsiu-Jen Lin, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20160343698
    Abstract: A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.
    Type: Application
    Filed: August 4, 2016
    Publication date: November 24, 2016
    Inventors: Meng-Tse Chen, Kuei-Wei Huang, Tsai-Tsung Tsai, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20160322339
    Abstract: A method of forming a package on package (PoP) structure includes forming a first die package, and bonding an external connector of a second die package to a solder paste layer of the first die package. The forming the first die package includes forming a contact pad over a substrate, attaching a metal ball with a convex surface to the contact pad, and applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste. The forming the first die package also includes attaching a semiconductor die to the substrate, and forming a molding compound between the semiconductor die and the metal ball, where the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound.
    Type: Application
    Filed: July 7, 2016
    Publication date: November 3, 2016
    Inventors: Kuei-Wei Huang, Wei-Yu Chen, Meng-Tse Chen, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9484285
    Abstract: A method for forming a device package includes forming a molding compound around a die and laminating a polymer layer over the die. A top surface of the die is covered by a film layer while the molding compound is formed, and the polymer layer extends laterally past edge portions of the die. The method further includes forming a conductive via in the polymer layer, wherein the conductive via is electrically connected to a contact pad at a top surface of the die.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: November 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chih-Wei Lin, Hui-Min Huang, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20160293588
    Abstract: A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.
    Type: Application
    Filed: June 20, 2016
    Publication date: October 6, 2016
    Inventors: Chih-Wei Lin, Ming-Da Cheng, Meng-Tse Chen, Wen-Hsiung Lu, Kuei-Wei Huang, Chung-Shi Liu
  • Publication number: 20160247782
    Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component coupled to a second package component by a first set of conductive elements. A first polymer-comprising material is arranged between the first package component and the second package component. The first polymer-comprising material surrounds the first set of conductive elements and the second package component. A third package component is coupled to the second package component by a second set of conductive elements. An underfill is arranged on the second package component and surrounds the second set of conductive elements. The first polymer-comprising material extends past sidewalls of the underfill.
    Type: Application
    Filed: May 2, 2016
    Publication date: August 25, 2016
    Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9425178
    Abstract: A method includes forming a first plurality of Redistribution Lines (RDLs) over a carrier, and bonding a device die to the first plurality of RDLs through flip-chip bonding. The device die and the first plurality of RDLs are over the carrier. The device die is molded in a molding material. After the molding, the carrier is detached from the first plurality of RDLs. The method further includes forming solder balls to electrically couple to the first plurality of RDLs, wherein the solder balls and the device die are on opposite sides of the first plurality of RDLs.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Shing-Chao Chen, Meng-Tse Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9418971
    Abstract: A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Kuei-Wei Huang, Tsai-Tsung Tsai, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9412717
    Abstract: Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Chun-Cheng Lin, Wen-Hsiung Lu, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20160211234
    Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Inventors: MENG-TSE CHEN, HSIU-JEN LIN, CHIH-WEI LIN, MING-DA CHENG, CHIH-HANG TUNG, CHUNG-SHI LIU
  • Patent number: 9397062
    Abstract: The described embodiments of mechanisms of forming a die package and package on package (PoP) structure involve forming a solder paste layer over metal balls of external connectors of a die package. The solder paste layer protects the metal balls from oxidation. In addition, the solder paste layer enables solder to solder bonding with another die package. Further, the solder paste layer moves an intermetallic compound (IMC) layer formed between the solder paste layer and the metal balls below a surface of a molding compound of the die package. Having the IMC layer below the surface strengthens the bonding structure between the two die packages.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Wei-Yu Chen, Meng-Tse Chen, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9373610
    Abstract: A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Ming-Da Cheng, Meng-Tse Chen, Wen-Hsiung Lu, Kuei-Wei Huang, Chung-Shi Liu
  • Publication number: 20160172348
    Abstract: A structure includes a first package component, and a second package component over and bonded to the first package component. A supporting material is disposed in a gap between the first package component and the second package component. A molding material is disposed in the gap and encircling the supporting material.
    Type: Application
    Filed: February 19, 2016
    Publication date: June 16, 2016
    Inventors: Yu-Chen Hsu, Yu-Feng Chen, Han-Ping Pu, Meng-Tse Chen, Guan-Yu Chen
  • Publication number: 20160148887
    Abstract: A device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die. The device package also includes an interconnect structure over the die. The interconnect structure includes a redistribution layer extending onto the molding compound and conformal to the non-planar surface of the molding compound. The device package further includes a first connector disposed over the die and bonded to the interconnect structure.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 26, 2016
    Inventors: Chen-Hua Yu, Meng-Tse Chen, Ming-Da Cheng, Chung-Shi Liu