Patents by Inventor Meng-Tse Chen

Meng-Tse Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Package-on-Package Structure and Method
    Publication number: 20180068985
    Abstract: A method includes attaching a first semiconductor package on a carrier, wherein the first semiconductor package comprises a plurality of stacked semiconductor dies and a plurality of contact pads, depositing a first molding compound layer over the carrier, wherein the first semiconductor package is embedded in the first molding compound layer, forming a plurality of vias over the plurality of contact pads, attaching a semiconductor die on the first molding compound layer, depositing a second molding compound layer over the carrier, wherein the semiconductor die and the plurality of vias are embedded in the second molding compound layer, forming an interconnect structure over the second molding compound layer and forming a plurality of bumps over the interconnect structure.
    Type: Application
    Filed: November 10, 2017
    Publication date: March 8, 2018
    Inventors: Sheng-Hsiang Chiu, Meng-Tse Chen, Ching-Hua Hsieh, Chung-Shi Liu, Sheng-Feng Weng, Ming-Da Cheng
  • Wafer Level Transfer Molding and Apparatus for Performing the Same
    Publication number: 20180043593
    Abstract: A method includes placing a package structure into a mold chase, with top surfaces of device dies in the package structure contacting a release film in the mold chase. A molding compound is injected into an inner space of the mold chase through an injection port, with the injection port on a side of the mold chase. During the injection of the molding compound, a venting step is performed through a first venting port and a second venting port of the mold chase. The first venting port has a first flow rate, and the second port has a second flow rate different from the first flow rate.
    Type: Application
    Filed: October 25, 2017
    Publication date: February 15, 2018
    Inventors: Bor-Ping Jang, Yeong-Jyh Lin, Chien Ling Hwang, Chung-Shi Liu, Meng-Tse Chen, Ming-Da Cheng, Chen-Hua Yu
  • Device Package with Reduced Thickness and Method for Forming Same
    Publication number: 20180033767
    Abstract: A device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die. The device package also includes an interconnect structure over the die. The interconnect structure includes a redistribution layer extending onto the molding compound and conformal to the non-planar surface of the molding compound. The device package further includes a first connector disposed over the die and bonded to the interconnect structure.
    Type: Application
    Filed: September 27, 2017
    Publication date: February 1, 2018
    Inventors: Chen-Hua Yu, Meng-Tse Chen, Ming-Da Cheng, Chung-Shi Liu
  • Manufacturing method of interconnect structure
    Patent number: 9881888
    Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: January 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Chih-Wei Lin, Ming-Da Cheng, Chih-Hang Tung, Chung-Shi Liu
  • STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES
    Publication number: 20180005973
    Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 4, 2018
    Inventors: Meng-Tse CHEN, Hsiu-Jen LIN, Chih-Wei LIN, Cheng-Ting CHEN, Ming-Da CHENG, Chung-Shi LIU
  • Package structure and method for forming the same
    Patent number: 9859229
    Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a first shielding feature over a base layer. The package structure also includes a package layer encapsulating the integrated circuit die and the first shielding feature. The package structure further includes a second shielding feature extending from the side surface of the base layer towards the first shielding feature to electrically connect to the first shielding feature. The side surface of the second shielding feature faces away from the side surface of the base layer and is substantially coplanar with the side surface of the package layer.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: January 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Peng Tsai, Sheng-Feng Weng, Sheng-Hsiang Chiu, Meng-Tse Chen, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Methods of packaging semiconductor devices and packaged semiconductor devices
    Patent number: 9847317
    Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Meng-Tse Chen, Hui-Min Huang, Chih-Fan Huang, Ming-Da Cheng
  • Advanced INFO POP and Method of Forming Thereof
    Publication number: 20170338202
    Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.
    Type: Application
    Filed: May 17, 2016
    Publication date: November 23, 2017
    Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Package-on-package structure and method
    Patent number: 9818729
    Abstract: A method includes attaching a first semiconductor package on a carrier, wherein the first semiconductor package comprises a plurality of stacked semiconductor dies and a plurality of contact pads, depositing a first molding compound layer over the carrier, wherein the first semiconductor package is embedded in the first molding compound layer, forming a plurality of vias over the plurality of contact pads, attaching a semiconductor die on the first molding compound layer, depositing a second molding compound layer over the carrier, wherein the semiconductor die and the plurality of vias are embedded in the second molding compound layer, forming an interconnect structure over the second molding compound layer and forming a plurality of bumps over the interconnect structure.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Hsiang Chiu, Meng-Tse Chen, Ching-Hua Hsieh, Chung-Shi Liu, Sheng-Feng Weng, Ming-Da Cheng
  • STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH FAN-OUT STRUCTURE
    Publication number: 20170316957
    Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes disposing a mold over the carrier substrate. The method further includes forming a protection layer between the mold and the carrier substrate to surround the semiconductor die and the conductive structures. In addition, the method includes removing the mold.
    Type: Application
    Filed: June 28, 2016
    Publication date: November 2, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shing-Chao CHEN, Chih-Wei LIN, Meng-Tse CHEN, Hui-Min HUANG, Ming-Da CHENG, Kuo-Lung PAN, Wei-Sen CHANG, Tin-Hao KUO, Hao-Yi TSAI
  • PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20170317038
    Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a first shielding feature over a base layer. The package structure also includes a package layer encapsulating the integrated circuit die and the first shielding feature. The package structure further includes a second shielding feature extending from the side surface of the base layer towards the first shielding feature to electrically connect to the first shielding feature. The side surface of the second shielding feature faces away from the side surface of the base layer and is substantially coplanar with the side surface of the package layer.
    Type: Application
    Filed: August 3, 2016
    Publication date: November 2, 2017
    Inventors: Yu-Peng TSAI, Sheng-Feng WENG, Sheng-Hsiang CHIU, Meng-Tse CHEN, Chih-Wei LIN, Wei-Hung LIN, Ming-Da CHENG, Ching-Hua HSIEH, Chung-Shi LIU
  • Wafer level transfer molding and apparatus for performing the same
    Patent number: 9802349
    Abstract: A method includes placing a package structure into a mold chase, with top surfaces of device dies in the package structure contacting a release film in the mold chase. A molding compound is injected into an inner space of the mold chase through an injection port, with the injection port on a side of the mold chase. During the injection of the molding compound, a venting step is performed through a first venting port and a second venting port of the mold chase. The first venting port has a first flow rate, and the second port has a second flow rate different from the first flow rate.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor-Ping Jang, Yeong-Jyh Lin, Chien Ling Hwang, Chung-Shi Liu, Meng-Tse Chen, Ming-Da Cheng, Chen-Hua Yu
  • Device package with reduced thickness and method for forming same
    Patent number: 9786631
    Abstract: A device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die. The device package also includes an interconnect structure over the die. The interconnect structure includes a redistribution layer extending onto the molding compound and conformal to the non-planar surface of the molding compound. The device package further includes a first connector disposed over the die and bonded to the interconnect structure.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Meng-Tse Chen, Ming-Da Cheng, Chung-Shi Liu
  • PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20170287865
    Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.
    Type: Application
    Filed: June 23, 2017
    Publication date: October 5, 2017
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin
  • Stud bump structure for semiconductor package assemblies
    Patent number: 9768137
    Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Chih-Wei Lin, Cheng-Ting Chen, Ming-Da Cheng, Chung-Shi Liu
  • Package on package structure and method for forming the same
    Patent number: 9711470
    Abstract: The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin
  • PACKAGE-ON-PACKAGE STRUCTURE HAVING POLYMER-BASED MATERIAL FOR WARPAGE CONTROL
    Publication number: 20170194289
    Abstract: The present disclosure relates to a package-on-package structure providing mechanical strength and warpage control. In some embodiments, the package-on-package structure includes a first set of conductive elements coupling a first package component to a second package component. A first molding material is arranged on the first package component. The first molding material surrounds the first set of conductive elements and outer sidewalls of the second package component and has a top surface below a top surface of the second package component. The stacked integrated chip structure further includes a second set of conductive elements that couples the second package component to a third package component.
    Type: Application
    Filed: March 17, 2017
    Publication date: July 6, 2017
    Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
  • Methods for forming fan-out package structure
    Patent number: 9691726
    Abstract: A method includes forming a first composite wafer including molding a plurality of device dies and a plurality of through-vias in a first molding material, and forming redistribution lines on opposite sides of the first molding material. The redistribution lines are inter-coupled through the plurality of through-vias. The method further includes forming a second composite wafer including stacking a plurality of dies to form a plurality of die stacks, and molding the plurality of die stacks in a second molding material. The second molding material fills gaps between the plurality of die stacks. The first composite wafer is bonded to the second composite wafer to form a third composite wafer.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Da Cheng, Hsien-Wei Chen, Cheng-Lin Huang, Meng-Tse Chen, Chung-Shi Liu
  • Singulation apparatus and method
    Patent number: 9679790
    Abstract: A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon. Each of the plurality of singulation sites includes a deformable portion and at least one vacuum hole. The at least one vacuum hole and the deformable portion is configured to form a seal around the at least one vacuum holes when a force is applied. The present disclosure further includes a method of manufacturing semiconductor devices, especially for a singulation process.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Cheng Lin, Yu-Peng Tsai, Meng-Tse Chen, Ming-Da Cheng, Chung-Shi Liu
  • Package on package bonding structure and method for forming the same
    Patent number: 9673182
    Abstract: A method of forming a package on package (PoP) structure includes forming a first die package, and bonding an external connector of a second die package to a solder paste layer of the first die package. The forming the first die package includes forming a contact pad over a substrate, attaching a metal ball with a convex surface to the contact pad, and applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste. The forming the first die package also includes attaching a semiconductor die to the substrate, and forming a molding compound between the semiconductor die and the metal ball, where the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Wei-Yu Chen, Meng-Tse Chen, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu