Patents by Inventor Meng-Tse Weng
Meng-Tse Weng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955460Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.Type: GrantFiled: October 5, 2020Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
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Patent number: 10615804Abstract: A clock and data recovery circuit includes a first phase detector, a first charge pump, a first voltage-controlled oscillator (VCO), and an auxiliary module. The auxiliary module includes: an auxiliary clock generator, generating an auxiliary clock signal; a second phase detector, coupled to the auxiliary clock generator, comparing a phase of the auxiliary clock signal with that of a first clock signal outputted by the first VCO; and a multiplexing selecting unit, outputting a multiplexing output signal to the first charge pump according to a selection signal.Type: GrantFiled: September 24, 2018Date of Patent: April 7, 2020Assignee: MEDIATEK INC.Inventors: Chien-Chung Wang, Meng-Tse Weng
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Publication number: 20190280696Abstract: A clock and data recovery circuit includes a first phase detector, a first charge pump, a first voltage-controlled oscillator (VCO), and an auxiliary module. The auxiliary module includes: an auxiliary clock generator, generating an auxiliary clock signal; a second phase detector, coupled to the auxiliary clock generator, comparing a phase of the auxiliary clock signal with that of a first clock signal outputted by the first VCO; and a multiplexing selecting unit, outputting a multiplexing output signal to the first charge pump according to a selection signal.Type: ApplicationFiled: September 24, 2018Publication date: September 12, 2019Inventors: Chien-Chung WANG, Meng-Tse WENG
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Patent number: 10355680Abstract: A frequency adjusting device includes a voltage droop detector and a frequency divider. The voltage droop detector compares a supply voltage with a lower threshold voltage to output a comparison result. When the supply voltage is greater than the threshold voltage, the frequency divider outputs a result of dividing a basic clock signal by a first value as a clock signal. When the supply voltage is smaller than the threshold voltage, the frequency divider outputs a result of dividing the basic clock signal by a second value as the clock signal.Type: GrantFiled: March 8, 2017Date of Patent: July 16, 2019Assignee: MSTAR SEMICONDUCTOR, INC.Inventor: Meng-Tse Weng
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Publication number: 20180062627Abstract: A frequency adjusting device includes a voltage droop detector and a frequency divider. The voltage droop detector compares a supply voltage with a lower threshold voltage to output a comparison result. When the supply voltage is greater than the threshold voltage, the frequency divider outputs a result of dividing a basic clock signal by a first value as a clock signal. When the supply voltage is smaller than the threshold voltage, the frequency divider outputs a result of dividing the basic clock signal by a second value as the clock signal.Type: ApplicationFiled: March 8, 2017Publication date: March 1, 2018Inventor: Meng-Tse Weng
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Patent number: 9685962Abstract: A clock data recovery apparatus includes an oscillator, a phase detector and an oscillator control circuit. The oscillator generates an original clock signal. The phase detector includes a first sampling circuit, a frequency dividing circuit, a second sampling circuit and a selecting circuit. The first sampling circuit samples a data signal using the original clock signal to generate a first set of sample results. The frequency dividing circuit divides the original clock signal to generate a frequency divided clock signal. The second sampling circuit performs sampling using the frequency divided clock signal to generate a second set of sample results. The selecting circuit selectively outputs one of the first and second sets of sample results as a final set of sample results. The oscillator control circuit controls the oscillator according to the final set of sample results.Type: GrantFiled: July 12, 2016Date of Patent: June 20, 2017Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Meng-Tse Weng, Chun-Wen Yeh, Jiunn-Yih Lee
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Patent number: 9673795Abstract: An integrated circuit includes a data sampler and a digital logic circuit. The data sampler provides multiple signal samples at a speed twice a symbol rate according to a local clock signal and the inverted local clock signal. The signal samples include a first symbol sample, and a second symbol sample that occurs later than the first symbol sample. The signal samples further include an interpolated sample between the first and second symbol samples. The digital logic circuit compares the first symbol sample with the interpolated sample to generate pre phase correction data, and compares the second symbol sample with the interpolated sample to generate post phase correction data. The pre phase correction data is generated earlier than the post phase correction data. The local clock signal and the inverted local clock signal have substantially a phase difference of 180 degrees.Type: GrantFiled: February 8, 2016Date of Patent: June 6, 2017Assignee: MStar Semiconductor, Inc.Inventors: Meng-Tse Weng, Jiunn-Yih Lee
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Publication number: 20170070230Abstract: A clock data recovery apparatus includes an oscillator, a phase detector and an oscillator control circuit. The oscillator generates an original clock signal. The phase detector includes a first sampling circuit, a frequency dividing circuit, a second sampling circuit and a selecting circuit. The first sampling circuit samples a data signal using the original clock signal to generate a first set of sample results. The frequency dividing circuit divides the original clock signal to generate a frequency divided clock signal. The second sampling circuit performs sampling using the frequency divided clock signal to generate a second set of sample results. The selecting circuit selectively outputs one of the first and second sets of sample results as a final set of sample results. The oscillator control circuit controls the oscillator according to the final set of sample results.Type: ApplicationFiled: July 12, 2016Publication date: March 9, 2017Inventors: Meng-Tse Weng, Chun-Wen Yeh, Jiunn-Yih Lee
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Publication number: 20170070218Abstract: An integrated circuit includes a data sampler and a digital logic circuit. The data sampler provides multiple signal samples at a speed twice a symbol rate according to a local clock signal and the inverted local clock signal. The signal samples include a first symbol sample, and a second symbol sample that occurs later than the first symbol sample. The signal samples further include an interpolated sample between the first and second symbol samples. The digital logic circuit compares the first symbol sample with the interpolated sample to generate pre phase correction data, and compares the second symbol sample with the interpolated sample to generate post phase correction data. The pre phase correction data is generated earlier than the post phase correction data. The local clock signal and the inverted local clock signal have substantially a phase difference of 180 degrees.Type: ApplicationFiled: February 8, 2016Publication date: March 9, 2017Inventors: Meng-Tse WENG, Jiunn-Yih LEE
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Publication number: 20170041009Abstract: A control method for a delay locked loop includes: delaying an input signal to generate an internal signal; delaying the internal signal to generate an output signal; and selectively providing a reference clock signal or the output signal as the input signal according to the output signal and the internal signal.Type: ApplicationFiled: December 2, 2015Publication date: February 9, 2017Inventors: Meng-Tse Weng, Hsian-Feng Liu, Chieh-Wen Lee
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Patent number: 9553593Abstract: A control method for a delay locked loop includes: delaying an input signal to generate an internal signal; delaying the internal signal to generate an output signal; and selectively providing a reference clock signal or the output signal as the input signal according to the output signal and the internal signal.Type: GrantFiled: December 2, 2015Date of Patent: January 24, 2017Assignee: MStar Semiconductor, Inc.Inventors: Meng-Tse Weng, Hsian-Feng Liu, Chieh-Wen Lee
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Patent number: 9419786Abstract: A multi-lane serial link signal receiving system includes a clock generating circuit and a plurality of data receiving channels. The clock generating circuit provides a fundamental clock signal. Each of the data receiving channels receives an input signal and the fundamental clock signal, and includes a phase detecting circuit, a multi-order digital clock data recovery circuit and a phase adjusting circuit. The phase detecting circuit samples the input signal according to a sampling clock signal to generate a sampled signal. The multi-order digital clock data recovery circuit performs a digital clock data recovery process on the sampled signal to generate phase adjusting information. The phase adjusting circuit adjusts the phase of the fundamental clock signal according to the phase adjusting information to generate the sampling clock signal.Type: GrantFiled: March 27, 2015Date of Patent: August 16, 2016Assignee: MStar Semiconductor, Inc.Inventors: Po-Nien Lin, Meng-Tse Weng, Jiunn-Yih Lee
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Publication number: 20150280761Abstract: A multi-lane serial link signal receiving system includes a clock generating circuit and a plurality of data receiving channels. The clock generating circuit provides a fundamental clock signal. Each of the data receiving channels receives an input signal and the fundamental clock signal, and includes a phase detecting circuit, a multi-order digital clock data recovery circuit and a phase adjusting circuit. The phase detecting circuit samples the input signal according to a sampling clock signal to generate a sampled signal. The multi-order digital clock data recovery circuit performs a digital clock data recovery process on the sampled signal to generate phase adjusting information. The phase adjusting circuit adjusts the phase of the fundamental clock signal according to the phase adjusting information to generate the sampling clock signal.Type: ApplicationFiled: March 27, 2015Publication date: October 1, 2015Inventors: Po-Nien Lin, Meng-Tse Weng, Jiunn-Yih Lee
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Patent number: 8791968Abstract: A source driver for driving at least one sub-pixel is disclosed, in which the source driver includes a gamma voltage generator and a digital to analog converter. The gamma voltage generator generates a plurality of gamma voltages, in which the gamma voltage generator includes a first gamma resistor string and an operation circuit. The first gamma resistor string includes a plurality of resistors electrically connected serially for dividing a first gamma reference voltage and a second gamma reference voltage into the gamma voltages. The operation circuit optionally adds increments to the gamma voltages according to a timing control signal, wherein the increments are the same when the gamma voltages are added. The digital to analog converter selecting one of the gamma voltages generated by the operation circuit as a driving voltage based on received digital pixel data.Type: GrantFiled: November 19, 2013Date of Patent: July 29, 2014Assignee: Himax Technologies LimitedInventors: Meng-Tse Weng, Chuan-Che Lee, Chin-Tien Chang, Chien-Ru Chen
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Patent number: 8729943Abstract: The present invention discloses a phase interpolating apparatus comprising: a first signal generation circuit, configured for generating a first signal having a first phase; an optional second signal generation circuit, configured for generating a second signal having the first phase; a third signal generation circuit, configured for generating a third signal having a second phase; a fourth/fifth signal generation circuit, configured for generating a fourth signal having a third phase when operating in a first mode and for generating a fifth signal having the second phase instead of the fourth signal when operating in a second mode; and a phase interpolator, configured for generating an interpolated signal without utilizing the fourth signal when operating in the first mode and for generating the interpolated signal according to the first signal, the third signal, and the fifth signal when operating in the second mode.Type: GrantFiled: May 2, 2013Date of Patent: May 20, 2014Assignee: MStar Semiconductor, Inc.Inventor: Meng-Tse Weng
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Publication number: 20140085357Abstract: A source driver for driving at least one sub-pixel is disclosed, in which the source driver includes a gamma voltage generator and a digital to analog converter. The gamma voltage generator generates a plurality of gamma voltages, in which the gamma voltage generator includes a first gamma resistor string and an operation circuit. The first gamma resistor string includes a plurality of resistors electrically connected serially for dividing a first gamma reference voltage and a second gamma reference voltage into the gamma voltages. The operation circuit optionally adds increments to the gamma voltages according to a timing control signal, wherein the increments are the same when the gamma voltages are added. The digital to analog converter selecting one of the gamma voltages generated by the operation circuit as a driving voltage based on received digital pixel data.Type: ApplicationFiled: November 19, 2013Publication date: March 27, 2014Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Meng-Tse Weng, Chuan-Che Lee, Chin-Tien Chang, Chien-Ru Chen
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Publication number: 20140021996Abstract: The present invention discloses a phase interpolating apparatus comprising: a first signal generation circuit, configured for generating a first signal having a first phase; an optional second signal generation circuit, configured for generating a second signal having the first phase; a third signal generation circuit, configured for generating a third signal having a second phase; a fourth/fifth signal generation circuit, configured for generating a fourth signal having a third phase when operating in a first mode and for generating a fifth signal having the second phase instead of the fourth signal when operating in a second mode; and a phase interpolator, configured for generating an interpolated signal without utilizing the fourth signal when operating in the first mode and for generating the interpolated signal according to the first signal, the third signal, and the fifth signal when operating in the second mode.Type: ApplicationFiled: May 2, 2013Publication date: January 23, 2014Applicant: MStar Semiconductor, Inc.Inventor: Meng-Tse Weng
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Patent number: 8605122Abstract: A gamma voltage generation circuit is provided. The gamma voltage generation circuit includes a plurality of resistor strings, a plurality of second resistors and a plurality of switches. Each of the resistor strings has a plurality of first resistors connected in series. Each of ends of the first resistors provides a gamma reference voltage. Each of second resistors is connected in series with the resistor strings. Each of the switches is coupled to a corresponding one of the resistor strings, selects and outputs one of the gamma reference voltages provided by the ends of the first resistors of the corresponding one of the resistor strings according to a control signal. Therefore, levels of the gamma voltages can synchronously displaced, so that the effects presented by pixels with different common voltage levels are similar or equal.Type: GrantFiled: January 19, 2010Date of Patent: December 10, 2013Assignee: Himax Technologies LimitedInventor: Meng-Tse Weng
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Patent number: 8547405Abstract: A gamma voltage generation circuit is provided. The gamma voltage generation circuit includes a resistor string, a first switch, and a second switch. The resistor string includes a plurality of resistors connected in series. An output terminal of the first switch is coupled to a first end of the resistor string. An output terminal of the second switch is coupled to a second end of the resistor string. The first switch selects and outputs one of a first high reference voltage and a second high reference voltage to the first end of the resistor string according to a control signal. The second switch selects and outputs one of a first low reference voltage and a second low reference voltage to the second end of the resistor string according to the control signal.Type: GrantFiled: January 19, 2010Date of Patent: October 1, 2013Assignee: Himax Technologies LimitedInventor: Meng-Tse Weng
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Patent number: 8493308Abstract: A source driver includes a plurality of first data channel pairs, a plurality of second data channel pairs, a first switch group, a second switch group, a third switch group, and a fourth switch group. Each of the first data channel pairs includes a first odd channel and a first even channel. The channels outputting voltages having the same polarity are short circuited together through the switch groups during a charge sharing period. As a result, the swings of the voltages of data lines coupled the corresponding channel are reduced, and further power consumption in the source driver could be reduced as compared with the related art.Type: GrantFiled: May 18, 2009Date of Patent: July 23, 2013Assignee: Himax Technologies LimitedInventor: Meng-Tse Weng