Abstract: The present disclosure includes a semiconductor package including a redistribution layer (RDL) having a first surface in contact with input/output (I/O) contacts and a second surface opposite to the first surface. The semiconductor package also includes a staircase interconnect structure formed on the second surface of the RDL and electrically connected with the RDL. The staircase interconnect structure includes staircase layers including a first staircase layer and a second staircase layer stacked on a top surface of the first staircase layer. The second staircase layer covers a portion of the top surface of the first staircase layer such that a remaining portion of the top surface of the first staircase layer is exposed. Integrated circuit (IC) chips are electrically connected to the RDL via the staircase interconnect structure. A first IC chip of the IC chips is electrically connected to the RDL through the remaining portion of the top surface of the first staircase layer.

Abstract: The present disclosure provides a method for displaying mark information performed by a computer device. The method includes: determining that a first virtual object controlled by a user of the computer device participates in a game task; displaying a preparation interface before the first virtual object enters a virtual game scene configured for the game task; after a target scene point in the virtual game is marked, displaying entry prompt information matching the target scene point in the preparation interface; and in response to an operation performed on an invitation control matching the target scene point, transmitting first entry invitation information to a second virtual object participating in the game task, the first entry invitation information including the target scene point for the second virtual object to follow the first virtual object in the game task.

Abstract: Provided is a display device, including: a display panel and a drive mainboard. The drive mainboard includes a first processor and a second processor. The second processor is electrically connected to the first processor and the display panel. The first processor is configured to acquire data of an image changed portion in response to a control instruction and output the data of the image changed portion to the second processor. The control instruction is issued for controlling a partial change of an image displayed on the display panel. The second processor is configured to output N slave input signals to the display panel. The N slave input signals carry the data of the image changed portion, wherein N is a positive integer greater than 1. The display panel is configured to perform partial image refresh based on the data of the image changed portion.

Abstract: The disclosure relates to an array substrate, a display panel, and a method for manufacturing an array substrate. The array substrate includes a first active layer on a substrate; a second active layer on a side of the first active layer away from the substrate; an intermediate layer between the first and second active layers and including a first via arriving at the first active layer, wherein the second active layer includes first, second and third sub-active layers, the first sub-active layer extending around a perimeter of the first via and in a direction away from the first via, the second sub-active layer covering a side wall of the first via, the third sub-active layer being at a bottom of the first via and covering a portion of a surface of the second active layer exposed by the first via, and wherein the second active layer is continuous.

Abstract: A display area of the array substrate only includes first sub-pixels capable of emitting light. In each two adjacent rows of first sub-pixels, a gate line electrically connected to one row of the plurality of rows of first sub-pixels and a reset signal line electrically connected to another row of the plurality of rows of first sub-pixels are electrically connected to the same first gate drive circuit. A target line electrically connected to a first row of the plurality of rows of first sub-pixels (i.e., another line other than the line electrically connected to the first gate drive circuit) is electrically connected to a second gate drive circuit. A target line electrically connected to a last row of the plurality of rows of first sub-pixels (i.e., another line other than the line electrically connected to the first gate drive circuit) is electrically connected to a third gate drive circuit.

Abstract: A display panel, including: a base substrate including an Under Display Camera (UDC) area and a normal display area located around a periphery of the UDC area, and specifically, the normal display area includes a plurality of sub-pixel driving circuits, and the UDC area includes a plurality of groups of sub-pixels, each of the plurality of groups of sub-pixels including at least two sub-pixels of a same color which have their anodes coupled to each other; and a plurality of first transparent wires, anodes in each group of sub-pixels coupled to a corresponding sub-pixel driving circuit among the plurality of sub-pixel driving circuits through a corresponding first transparent wire among the plurality of first transparent wires.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, a plurality of pixels, a plurality of gate lines and a plurality of data lines, wherein the base substrate has a plurality of transparent regions and a plurality of display regions; the pixels are on the base substrate and within the display regions; each pixel includes a plurality of sub pixels; the sub pixels of each pixel are divided into two rows of sub pixels; the gate lines and the data lines are on the base substrate; the sub pixels of a first pixel are connected with the same gate line; the gate line connected with the sub pixels of the first pixel is between the two rows of sub pixels of the first pixel; and the first pixel is any one of the plurality of pixels.

Abstract: The application relates to the technical field of artificial intelligence, and provides a method, device, electronic equipment and storage medium for positioning macular center in fundus images. The method comprises: acquiring a detection result of the fundus image detection model, wherein the detection result includes an optic disc area, and a first detection block and a first confidence score corresponding to the optic disc area, and a macular area, and a second detection block and a second confidence score corresponding to the macular area; calculating a center point coordinate of the optic disc area according to the first detection block, and calculating a center point coordinate of the macular area according to the second detection block; identifying whether the to-be-detected fundus image is a left eye fundus image or a right eye fundus image, and correcting a center point of the macular area using different correction models.

Abstract: The invention introduces a system for acquiring data on poultry body size, utilizing a baseplate for immobilization. After positioning the poultry, the system adjusts a fixing device on a rod to secure the poultry's knee joints using a fixing clip, thereby stabilizing the poultry's body. A 3D laser scanning lens then conducts comprehensive 3D scanning of the poultry's entire body, transmitting the data to a 3D microcomputer which generates an optimal dynamic model image. This microcomputer organizes and analyzes data from the model using a computer algorithm, ultimately displaying the poultry's body size indices on the 3D microcomputer's display. This method circumvents inaccuracies common with traditional tools like electronic scales, enhancing the speed and precision of poultry body composition data collection.

Abstract: The present application provides a structure of HR-SOI embedded with a charge capture layer and manufacture thereof. The process for manufacturing a structure of HR-SOI embedded with a charge capture layer comprises: providing a first substrate, wherein the first substrate has a first surface, and a pinning layer is formed on the first surface by a deposition process, and homogenizing the pinning layer surface by dry etching to adjust a thickness uniformity of the pinning layer. Accordingly, the thickness uniformity of the obtained polysilicon film is able to reach a good state.

Abstract: The present application provides a structure of HR-SOI embedded with a charge capture layer and manufacture thereof. The process for manufacturing a structure of HR-SOI embedded with a charge capture layer comprises: providing a first substrate, wherein the first substrate has a first surface to be subjected to a roughness treatment to form an uneven morphology on the first surface; forming a surface treatment layer, wherein the surface treatment layer has an uneven surface morphology; and forming a polysilicon layer on the surface treatment layer. By the roughness treatment to the first substrate, the first surface and the surface treatment layer both have uneven surface morphology, such that the formed polysilicon layer has stable orientation evolution and grain size, and an increased grain boundary density. Thereby a highly efficient charge trapping polysilicon film can be obtained.

Abstract: One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N NMOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.

Abstract: A method for fabricating a semiconductor device includes: forming a fin-based structure protruding from a top boundary of a substrate; forming a first nanosheet-based structure protruding from the top boundary of the substrate; epitaxially growing a first, a second, and a third source/drain (S/D) regions, the first S/D region disposed between the fin-based structure and the first nanosheet-based structure, the second S/D region disposed opposite the fin-based structure from the first S/D region, and the third S/D region disposed opposite the first nanosheet-based structure from the first S/D region, and the first to the third S/D regions having a same conductive type; forming a second nanosheet-based structure protruding from the boundary of the substrate and laterally spaced apart from the first nanosheet-based structure; and epitaxially growing a fourth S/D region disposed opposite the second nanosheet-based structure from the third S/D region.

Abstract: The present application relates to a RAID optimization method and apparatus for Multi-Pass NAND programming, a computer device, and a storage medium. The method includes: obtaining a RAID optimization request for the Multi-Pass NAND programming; performing, by a RAID engine, encoding on cached user data of a corresponding RAID stripe during each Pass programming, according to the RAID optimization request of the Multi-Pass NAND programming; generating corresponding Parity data in real time through the encoding by the RAID engine; releasing a buffer area for storing the Parity after a corresponding Pass programming is completed, without waiting until all-Passes programming has been completed. According to the present application, aiming at a Multi-Pass programming scenario, RAID parity data is dynamically generated without buffering the corresponding parity data during each pass programming.

Abstract: A load recovery method and system for a power distribution network (PDN) considering standby energy storage of 5G base stations (BSs) is disclosed, falling within the field of power systems. The method includes constructing a basic model of a 5G BS; evaluating a schedulable capacity of a standby battery of the 5G BS; modeling operation behaviors of the 5G BS at different stages after a power outage of the PDN; using a double-layer optimization model to describe the load recovery of the PDN for the 5G BS on the basis of the correlation between the operation behaviors of the 5G BS and a load recovery process in practice; and solving the double-layer optimization model to complete the load recovery of a PDN system. The problem that no research has focused on how to use the 5G BSs to enhance the resilience of PDN is solved.

Abstract: A micro-zone soil sampling apparatus and method for different contamination situations. The apparatus includes an uncovered cylinder and a plurality of circular separators. The circular separators are vertically arranged in a hollow inner cavity of the uncovered cylinder, and are removably connected to an inner wall of the uncovered cylinder. Each circular separator includes a plurality of inner rings arranged coaxially, an outer ring coaxially arranged outside the inner rings, and a soil-bearing net. Each circular separator is divided into multiple hollow spaces by the inner rings and the outer ring. The inner rings made of a permeable membrane material and the outer ring made of a rigid material both have a certain thickness. The soil-bearing net is fittedly fixed on a bottom of each circular separator. A plurality of spokes passing through a center of the soil-bearing net are fixedly arranged on the soil-bearing net.

Abstract: The invention provides a mechanical drum suspension pull turn-up molding structure.

Abstract: The present disclosure discloses nitrosamine impurities, a varenicline pharmaceutical composition capable of reducing the generation of nitrosamine impurities, and the preparation and use thereof. By means of adding a pharmaceutically acceptable acid to a secondary amine compound or a composition thereof, the pharmaceutical composition of the present disclosure can effectively inhibit and reduce the generation of nitrosamine impurities, improve the stability of the secondary amine compound or the composition thereof, and control the content of genotoxic nitrosamine impurities to be at a relatively low level, so as to comply with safety requirements.

Abstract: Provided is a class of compounds with methyltransferase inhibitory activity. Specifically, provided is a class of compounds with PRMT5 inhibitory activity. The compounds can be used for preparing a pharmaceutical composition for treating PRMT5 activity-related diseases.