Abstract: Embodiments of the present disclosure provide a solution for video generation. The method comprises: determining a video feature of an input video and a text feature of an input text; dividing the video feature into a plurality of 3D video windows based on a predetermined window size, the plurality of 3D video windows comprising a first video window and a second video window; updating the video feature by determining video attention within each video window of the plurality of 3D video windows, wherein the video attention associated with the first video window is independent from the second video window; and generating a target video based on the updated video feature.

Abstract: A write operation initiated by a memory sub-system controller of a memory sub-system to write system metadata to one or more of a plurality of dies of the a memory sub-system is identified by a processing device. A redundancy die of a plurality of dies of the memory sub-system is identified. One or more first physical blocks of the redundancy die is identified. A first write operation to write the system metadata to the one or more first physical blocks is performed.

Abstract: A memory sub-system controller performs garbage collection on flexible data placement (FDP) compliant memory sub-systems, such as solid state drives (SSDs). The controller stores a set of data across a plurality of memory components of a set of memory components, a first of the plurality of components being configured to store data in a first set of regions using a first write cursor, and a second of the plurality of components being configured to store data in a second set of regions using a second write cursor. The controller programs data, received from a host system, in a first portion of the first set of regions using the first write cursor. The controller relocates previously programmed data from a second portion of the first set of regions to the first portion of the first set of regions using the first write cursor.

Abstract: A pose determining method, which may be applied to the field of photographing and image processing, includes: obtaining a target image, where the target image includes a target parking space mark and a target parking space line, and a target parking space corresponding to the target parking space mark includes the target parking space line; and determining pose information based on the target parking space mark and the target parking space line. The pose information indicates a corresponding pose of a terminal during photographing of the target image. According to the pose determining method, the pose information may be determined based on the target parking space mark and the target parking space line, to implement positioning.

Abstract: Aspects of the present disclosure configure a memory sub-system controller to balance program-erase count (PEC) across multiple reclaim groups of a memory sub-system. The controller groups a set of memory components into a plurality of reclaim groups (RGs), each RG of the plurality of RGs comprising a subset of reclaim units (RUs). The controller receives a request to program a set of data into a first RG of the plurality of RGs and compares a first PEC of the first RG with a second PEC of a second RG of the plurality of RGs. The controller performs wear leveling operations for the set of data requested to be programmed into the first RG using one or more memory components associated with the second RG based on a result of comparing the first PEC of the first RG with the second PEC of the second RG.

Abstract: This disclosure is directed to a memory device that performs garbage collection (GC) operations intelligently. The memory device generates a request to perform a GC operation on data stored on the memory device and, in response, accesses a valid translation unit count (VTC) velocity of each portion of a plurality of portions of the data stored on the memory device. The memory device selects an individual portion of the plurality of portions based on the VTC velocity of the individual portion and performs the GC operation on the selected individual portion.

Abstract: In some implementations, a memory device may receive a write command that includes data to be written to multiple memory pages of a translation unit (TU) of the memory device. The multiple memory pages of the TU may span multiple memory planes of the memory device. The memory device may identify the multiple memory pages of the TU, to which the data is to be written, based on one or more bad blocks of the memory device and a determination of whether one or more memory pages of the memory device are to be reserved. The memory device may write the data to the multiple memory pages of the TU.

Abstract: A power loss protection failure is detected at a memory device. Based on detecting the power loss protection failure, a count of unused entries in a journal buffer is determined. A host command is received, and a number of entries needed to record the host command to the journal buffer is determined. In response to determining the count of unused entries in the journal buffer includes a least the number of entries needed to record the host command to the journal buffer, the host command is recorded in the journal buffer and the count of unused entries is reduced by the number of entries needed to record the host command to the journal buffer.

Abstract: Aspects of the present disclosure configure a memory sub-system controller to fold data based on valid translational unit count (VTC) values in a memory sub-system. The controller receives a request to perform a folding operation on data stored in an individual block stripe of the set of memory components. The controller retrieves, from a VTC table, a plurality of VTC values corresponding to a plurality of portions of the individual block stripe. The controller compares a first VTC value of the plurality of VTC values associated with a first of the plurality of portions to a second VTC value of the plurality of VTC values associated with a second of the plurality of portions. The controller performs the folding operation on a subset of the plurality of portions based on a result of comparing the first VTC value to the second VTC value.

Abstract: Aspects of the present disclosure configure a memory sub-system controller, to balance PEC across dies/planes of a memory sub-system. The memory sub-system controller determines that a first PEC of a first portion of a set of memory components is smaller than a second lifetime PEC of a second portion of the set of memory components. The memory sub-system controller performs a first memory operation on the first and second portions in response to a first request associated with the block stripe. The memory sub-system controller erases the block stripe comprising the first and second portions. The memory sub-system controller performs a second memory operation on the second portion of the set of memory components without performing the second memory operation on the first portion of the set of memory components in response to a second request associated with the block stripe.

Abstract: Aspects of the present disclosure configure a memory sub-system controller to fold data based on valid translational unit count (VTC) values in a memory sub-system. The controller receives a request to perform a folding operation on data stored in an individual block stripe of the set of memory components. The controller retrieves, from a VTC table, a plurality of VTC values corresponding to a plurality of portions of the individual block stripe. The controller compares a first VTC value of the plurality of VTC values associated with a first of the plurality of portions to a second VTC value of the plurality of VTC values associated with a second of the plurality of portions. The controller performs the folding operation on a subset of the plurality of portions based on a result of comparing the first VTC value to the second VTC value.

Abstract: In some implementations, a memory device may receive a write command that includes data to be written to multiple memory pages of a translation unit (TU) of the memory device. The multiple memory pages of the TU may span multiple memory planes of the memory device. The memory device may identify the multiple memory pages of the TU, to which the data is to be written, based on one or more bad blocks of the memory device and a determination of whether one or more memory pages of the memory device are to be reserved. The memory device may write the data to the multiple memory pages of the TU.

Abstract: A processing device in a memory sub-system receives a request to write data to a memory device, the request comprising a data item and a logical address. The processing device allocates a plurality of pages of the memory device to a page set, wherein the plurality of pages are associated with a same block of the memory device and sequentially numbered within the same block. The processing device writes the data to the page set and modifies, in an address translation data structure (ATDS), a logical address mapping of a translation unit (TU) associated with the page set.

Abstract: A processing device in a memory sub-system receives a request to write data to the memory device, wherein the memory device is configured to store a first number of bits per memory cell. The processing device obtains a temperature measurement of the memory device. Responsive to determining that the temperature measurement of the memory device satisfies a first operating temperature threshold criterion, the processing device reconfigures the memory device to store a second number of bits per memory cell, wherein the first operating temperature threshold criterion is associated with the first number of bits per memory cell, and wherein the second number of bits per memory cell is less than the first number of bits per memory cell. The processing device performs a write operation to store the data in the memory device using the second number of bits per memory cell.

Abstract: A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.

Abstract: A method includes assigning a respective initial credit value to each LUN of a block stripe; performing an erase operation across the block stripe; reducing, in response to the erase operation, each respective initial credit value by a unit increment to provide a respective reduced credit value; refraining from programming to each LUN of the block stripe having a respective reduced credit value equal to zero; and programming to each LUN of the block stripe having a respective reduced credit value greater than zero.

Abstract: A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to perform operations including setting a partial translation unit (TU) pointer to identify a first partial-TU of an ordered sequence of partial-TUs, the ordered sequence spanning over a plurality of dies of the memory device. The operations further include, responsive to determining that the first partial-TU has a good health status, appending the first partial-TU to a partial-TU stripe and incrementing the partial-TU pointer to identify a second partial-TU. The operations further include, responsive to determining that the second partial-TU has a bad health status, incrementing the partial-TU pointer without adding the second partial-TU to the partial-TU stripe. The operations further include performing one or more write operations on a plurality of TUs comprised by the partial-TU stripe.

Abstract: A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.

Abstract: Disclosed herein are methods, apparatuses and systems related to adjusting operation of memory dies according to reliability measures determined in real-time. The apparatus may be configured to determine the reliability measures based on (1) initiating and completing a programming operation within respective timings following an erase operation and (2) reading the programmed data within a window from completing the programming operation.

Abstract: A method includes assigning a respective initial credit value to each LUN of a block stripe; performing an erase operation across the block stripe; reducing, in response to the erase operation, each respective initial credit value by a unit increment to provide a respective reduced credit value; refraining from programming to each LUN of the block stripe having a respective reduced credit value equal to zero; and programming to each LUN of the block stripe having a respective reduced credit value greater than zero.