Abstract: Disclosed herein are methods, apparatuses and systems related to adjusting operation of memory dies according to reliability measures determined in real-time. The apparatus may be configured to determine the reliability measures based on (1) initiating and completing a programming operation within respective timings following an erase operation and (2) reading the programmed data within a window from completing the programming operation.

Abstract: There is provided a phase shifter having a phase shift region and a peripheral region, and including a first substrate, a second substrate and a dielectric layer between such two substrates; the first substrate includes a first dielectric substrate, a first electrode and a first auxiliary structure; the second substrate includes a second dielectric substrate, a second electrode and a second auxiliary structure; the phase shift region includes overlapping regions; the first electrode and the second electrode are located in the phase shift region, and have orthographic projections, on the first dielectric substrate, overlapped at least partially in the overlapping regions; the first auxiliary structure is in the peripheral region and on a side, close to the dielectric layer, of the first dielectric substrate; the second auxiliary structure is in the peripheral region and on a side, close to the dielectric layer, of the second dielectric substrate.

Abstract: The present disclosure provides a single-channel test device. The single-channel test device includes a metal flange, and a waveguide-coaxial conversion structure and a first square straight waveguide which are disposed along a central axis of the metal flange and disposed on two opposite sides of the metal flange respectively, wherein in the case that a waveguide aperture of one end of the first square straight waveguide distal to the metal flange is placed on and is kept in close contact with a single antenna unit to be tested in a phased reflectarray to be tested, the single-channel test device is configured to test a scattering parameter of the antenna unit to be tested.

Abstract: A semiconductor device package includes a carrier, an emitting element and a first package body. The carrier includes a first surface and a second surface opposite to the first surface. The emitting element is disposed on the first surface of the carrier. The first package body is disposed over the first surface of the carrier and spaced apart from the first surface of the carrier.

Abstract: A method is disclosed to dynamically design acceleration units of neural networks. The method comprises steps of generating plural circuit description files through a neural network model; reading a model weight of the neural network model to determine a model data format of the neural network model; selecting one circuit description file from the plural circuit description files according to the model data format, so that the chip is reconfigured according to the selected circuit description file to form an acceleration unit adapted to the model data format. The acceleration unit is suitable for running a data segmentation algorithm, which may accelerate the inference process of the neural network model. Through this method the chip may be dynamically reconfigured into an efficient acceleration unit for the different model data format, thereby speeding up the inference process of the neural network model.

Abstract: Semiconductor devices and method of manufacture are provided. In embodiments a conductive connector is utilized to provide an electrical connection between a substrate and an overlying shield. The conductive connector is placed on the substrate and encapsulated with an encapsulant. Once encapsulated, an opening is formed through the encapsulant to expose a portion of the conductive connector. The shield is deposited through the encapsulant to make an electrical connection to the conductive connector.

Abstract: A semiconductor device package includes a first circuit layer, a first emitting device and a second emitting device. The first circuit layer has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the first circuit layer. The first emitting device has a first surface facing the first circuit layer and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device.

Abstract: Provided is a method for tracking a satellite. The method includes: acquiring trajectory information and antenna attitude information of a COTM device; calculating a theoretical pointing angle of an antenna beam for a target satellite based on an orbit parameter of the target satellite and the trajectory information; acquiring an actual pointing angle of the antenna beam by correcting, based on the antenna attitude information, the theoretical pointing angle of the antenna beam; controlling, based on the actual pointing angle of the antenna beam, a receiving phased array antenna to form an antenna beam; acquiring data information of the satellite signal, and correcting an actual pointing angle of the current antenna beam; controlling a transmitting phased array antenna to form an antenna beam based on a corrected actual pointing angle; establishing a communication link and updating ephemeris data of the target satellite.

Abstract: Exemplary methods, apparatuses, and systems include erasing a portion of memory from a garbage pool in response to detecting an idle period. A request to write data to the memory is received and it is determined that a charge gain threshold has not been satisfied for the erased portion of memory. The data is written to the erased portion of memory in response to determining the charge gain threshold has not been satisfied.

Abstract: A processing device identifies a first set of bits associated with a translation unit of a memory device, wherein the first set of bits correspond to a page field; identifies a second set of bits associated with the translation unit, wherein the second set of bits corresponds to a block field; updates a first portion of an address mapping table corresponding to the second set of bits with a value representing a difference between a value stored in the page field and a threshold value; updates a second portion of the address mapping table corresponding to the first set of bits with a value representing a block number; determines, based on the updated first portion and the updated second portion, that a swapping condition is satisfied; and performs a data access operation on a set of memory cells residing at a location corresponding to the translation unit.

Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Abstract: Aspects of the present disclosure configure a memory sub-system controller to balance program-erase count (PEC) across multiple reclaim groups of a memory sub-system. The controller groups a set of memory components into a plurality of reclaim groups (RGs), each RG of the plurality of RGs comprising a subset of reclaim units (RUs). The controller receives a request to program a set of data into a first RG of the plurality of RGs and compares a first PEC of the first RG with a second PEC of a second RG of the plurality of RGs. The controller performs wear leveling operations for the set of data requested to be programmed into the first RG using one or more memory components associated with the second RG based on a result of comparing the first PEC of the first RG with the second PEC of the second RG.

Abstract: A sound signal processing includes obtaining sound signals; amplifying the sound signals based on a plurality of analog gain values to generate a plurality of amplified sound signals, where each amplified sound signal corresponds to a respective analog gain value; digitizing the plurality of amplified sound signals to produce plurality of digital sound signals; determining whether the plurality of digital sound signals are clipped or non-clipping, and selectively outputting the non-clipping sound signals; and applying a dynamic range control program to the non-clipping sound signals to adjust them.

Abstract: Semiconductor devices and method of manufacture are provided. In embodiments a conductive connector is utilized to provide an electrical connection between a substrate and an overlying shield. The conductive connector is placed on the substrate and encapsulated with an encapsulant. Once encapsulated, an opening is formed through the encapsulant to expose a portion of the conductive connector. The shield is deposited through the encapsulant to make an electrical connection to the conductive connector.

Abstract: A waveguide probe structure, a calibration device for an antenna array and a calibration method for an antenna array are provided. The waveguide probe structure includes a waveguide coaxial converter, a tapered waveguide and a first straight waveguide. The waveguide coaxial converter is configured to transmit and receive two orthogonal linearly-polarized signals; the tapered waveguide includes a first waveguide cavity including a first waveguide port and a second waveguide port, the first waveguide port is connected to the waveguide coaxial converter, the second waveguide port is connected to the first straight waveguide, and a size of a cross section of the first waveguide cavity increases monotonically in a direction from the first waveguide port to the second waveguide port; the first straight waveguide includes a second waveguide cavity, a size of a cross section of the second waveguide cavity is equal to a size of the second waveguide port.

Abstract: Exemplary methods, apparatuses, and systems include erasing a portion of memory from a garbage pool in response to detecting an idle period. A request to write data to the memory is received and it is determined that a charge gain threshold has not been satisfied for the erased portion of memory. The data is written to the erased portion of memory in response to determining the charge gain threshold has not been satisfied.

Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

Abstract: A phase calibration method for a phased array antenna is provided. The method includes: sequentially calibrating M×N antenna units based on a pre-obtained test voltage set including first test voltages; sequentially loading the first test voltages to the antenna unit in the ith row and the jth column, and acquiring phase and amplitude information of a microwave signal radiated by the antenna unit every time one first test voltage is loaded; acquiring first array vectors through analysis based on the phase and amplitude information of the acquired microwave signals of the antenna unit under different first test voltages; obtaining a calibration response vector of the antenna unit under each first test voltage in the test voltage set through a first preset algorithm based on the first array vector, and determining a target voltage-phase curve corresponding to the antenna unit in the ith row and the jth column.

Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.