Abstract: The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate having an opening over the contact pad; and a conductive pillar over the opening of the passivation layer, wherein the conductive pillar comprises an upper portion substantially perpendicular to a surface of the substrate and a lower portion having tapered sidewalls.

Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.

Abstract: A method of forming a device includes forming an under-bump metallurgy (UBM) layer including a barrier layer and a seed layer over the barrier layer; and forming a mask over the UBM layer. The mask covers a first portion of the UBM layer, and a second portion of the UBM layer is exposed through an opening in the mask. The first portion of the UBM layer includes a barrier layer portion and a seed layer portion. A metal bump is formed in the opening and on the second portion of the UBM layer. The mask is then removed. A wet etch is performed to remove the seed layer portion. A dry etch is performed to remove the barrier layer portion.

Abstract: A method of forming an integrated circuit structure includes forming a copper-containing seed layer on a wafer, and performing a descum step on an exposed surface of the copper-containing seed layer. The descum step is performed using a process gas including fluorine and oxygen. A reduction/purge step is then performed on the exposed surface of the copper-containing seed layer using a nitrogen-containing gas. A copper-containing layer is plated on the copper-containing seed layer.