Patents by Inventor Meng Yi

Meng Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230024339
    Abstract: A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.
    Type: Application
    Filed: February 9, 2022
    Publication date: January 26, 2023
    Inventors: Chih-Hsuan Cheng, Chieh-Fang Chen, Sheng-Chen Wang, Chieh-Yi Shen, Han-Jong Chia, Feng-Ching Chu, Meng-Han Lin, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11551967
    Abstract: Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Pei Lu, Ming-Han Lee, Shin-Yi Yang, Tz-Jun Kuo
  • Patent number: 11545619
    Abstract: A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsing-Hsiang Wang, Han-Ting Lin, Yu-Feng Yin, Sin-Yi Yang, Chen-Jung Wang, Yin-Hao Wu, Kun-Yi Li, Meng-Chieh Wen, Lin-Ting Lin, Jiann-Horng Lin, An-Shen Chang, Huan-Just Lin
  • Publication number: 20220400966
    Abstract: A method for presenting data of blood-pressure measurement includes: calculating blood-pressure index values based on entries of data of blood-pressure measurement; and presenting a blood-pressure trend interface that includes index level regions, and for each of the blood-pressure index values, an index level markers disposed in one of the index level regions. The blood-pressure trend interface is presented in a manner that the index level markers corresponding respectively to the blood-pressure index values cooperatively indicate a trend in the blood pressure.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 22, 2022
    Inventor: Meng-Yi LIN
  • Publication number: 20220391061
    Abstract: A portable electronic device and a one-hand touch operation method thereof are provided. A touch operation performed on a touch screen is detected. When a shift amount of the touch operation in a first direction is greater than a first threshold, whether to activate a one-hand mode is determined according to a shift amount of the touch operation in a second direction. When the one-hand mode is activated, the operation interface image is zoomed out or shifted, and displayed in a one-hand mode interface display region.
    Type: Application
    Filed: May 24, 2022
    Publication date: December 8, 2022
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Meng Chen Hsieh, CHEN-YU HSU, Chih-Hsien Yang, I-Hsi Wu, HSIN-YI PU
  • Publication number: 20220379311
    Abstract: A cell purification module, configured to purify multiple cells from a fluid sample is provided. The cell purification module includes a hollow column, multiple hollow fiber membranes, at least one first magnetic component, a fluid sample inlet end, and a fluid sample outlet end. The hollow column has a first opening, a second opening, and an accommodating space connecting the first opening and the second opening. The hollow fiber membranes are disposed in the accommodating space and each hollow fiber membrane has multiple pores. The first magnetic component is disposed at a periphery of the hollow column. The fluid sample inlet end and the fluid sample outlet end are respectively disposed at two ends of the hollow column. The hollow fiber membranes extend in an axial direction of the hollow column, and are arranged in a radial direction of the hollow column. A cell purification system is also provided.
    Type: Application
    Filed: May 26, 2022
    Publication date: December 1, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Lih-Tao Hsu, Shen-Hua Peng, Cheng-Yi Wu, Jeng-Liang Kuo, Meng-Hsueh Lin, Chih-Chieh Huang, Wei-Lin Yu, Hui-Ting Huang
  • Patent number: 11508668
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Meng-Wei Hsieh, Yu-Pin Tsai
  • Publication number: 20220364236
    Abstract: In an embodiment, an apparatus includes: a susceptor including substrate pockets; a gas injector disposed over the susceptor, the gas injector having first process regions, the gas injector including a first gas mixing hub and first distribution valves connecting the first gas mixing hub to the first process regions; and a controller connected to the gas injector and the susceptor, the controller being configured to: connect a first precursor material and a carrier gas to the first gas mixing hub; mix the first precursor material and the carrier gas in the first gas mixing hub to produce a first precursor gas; rotate the susceptor to rotate a first substrate disposed in one of the substrate pockets; and while rotating the susceptor, control the first distribution valves to sequentially introduce the first precursor gas at each of the first process regions as the first substrate enters each first process region.
    Type: Application
    Filed: July 14, 2022
    Publication date: November 17, 2022
    Inventors: Yung-Chang Chang, Meng-Yin Tsai, Tung-Hsiung Liu, Liang-Yu Yeh, Chun-Yi Lee, Kuo-Hsi Huang
  • Publication number: 20220359413
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and is adjacent to the first conductive feature. The first and second conductive features are separated by a cavity. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the cavity and further extends along opposing sidewalls of the first and second conductive features. A dielectric cap covers and seals the cavity. The dielectric cap has a top surface that is approximately planar with top surfaces of the first and second conductive features. The first conductive feature and the second conductive feature comprise graphene intercalated with one or more metals.
    Type: Application
    Filed: May 5, 2021
    Publication date: November 10, 2022
    Inventors: Shin-Yi Yang, Meng-Pei Lu, Chin-Lung Chung, Ming-Han Lee, Shau-Lin Shue
  • Publication number: 20220359425
    Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.
    Type: Application
    Filed: May 24, 2022
    Publication date: November 10, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Chiang SHIH, Hung-Yi LIN, Meng-Wei HSIEH, Yu Sheng CHANG, Hsiu-Chi LIU, Mark GERBER
  • Publication number: 20220359378
    Abstract: A method for forming a semiconductor structure includes following operations. A hybrid layered structure is formed. The hybrid layered structure includes at least a 2D material layer and a first 3D material layer. Portions of the hybrid layered structure are removed to form a plurality of conductive features and at least an opening between the conductive features. A dielectric material is formed to fill the opening and to form an air gap sealed within.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: MENG-PEI LU, SHIN-YI YANG, SHU-WEI LI, CHIN-LUNG CHUNG, MING-HAN LEE
  • Publication number: 20220352012
    Abstract: Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.
    Type: Application
    Filed: July 19, 2022
    Publication date: November 3, 2022
    Inventors: Meng-Pei LU, Tz-Jun Kuo, Shin-Yi Yang, Ming-Han Lee
  • Patent number: 11478176
    Abstract: In a microrunner structure, there are provided with components for a cleaning procedure required to conduct electrochemical sensing when a biosensor is activated for sensing; and a urine signal detection device that is a SoC (System on a Chip), which has a wireless transceiving circuit for receiving a urine measurement method and channel information transmitted from an intelligent device, and in turn, outputting a stimulus signal to trigger a biosensor or a non-biosensor in a multi-channel structure to conduct urine sense processing for a sensing area, as well as transmitting detection processing for a concentration of urine substances from the electrochemical sensing to the intelligent device through the wireless transceiving circuit to assess a risk index between a heart disease or diabetes and a kidney disease.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: October 25, 2022
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Shuenn-Yuh Lee, Ju-Yi Chen, Meng-Dar Shieh, Chia-Yu Lin, Yu-Jin Lin, Ding-Siang Ciou
  • Patent number: 11446885
    Abstract: Disclosed is a friction-reducing and anti-wear composite material for a wading kinematic pair and a method of preparing the same. The friction-reducing and anti-wear composite material is prepared from carbon fiber (CF) among inorganic fillers, polyimide (PI) and polyether ether ketone (PEEK). These three materials are wet-mixed, dried and placed in a mold followed by curing by a heat press. The cured product is cooled and demolded to obtain the CF/PI/PEEK friction-reducing and anti-wear composite material for a wading kinematic pair. Tribological properties of the PEEK material are enhanced due to synergistic effect arising from hybrid organic-inorganic filling. The friction-reducing and anti-wear composite material provided in the invention has significantly reduced friction coefficient and wear volume loss under the seawater environment.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: September 20, 2022
    Assignee: Wuhan Research Institute Of Materials Protection
    Inventors: Haitao Duan, Tian Yang, Jian Li, Meng Yi, Jiesong Tu, Dan Jia, Shengpeng Zhan, Yongliang Jin, Jianwei Qi
  • Publication number: 20220271087
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. A substrate having a cell region and a mark region is received. A dielectric layer is etched to expose a conductive line in the cell region and form a trench in the mark region. A conductive layer is formed over the cell region and in the trench. The conductive layer is etched to form a bottom electrode via in the cell region and a first mark layer in the trench.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 25, 2022
    Inventors: HAN-TING LIN, JIANN-HORNG LIN, HSING-HSIANG WANG, HUAN-JUST LIN, SIN-YI YANG, CHEN-JUNG WANG, KUN-YI LI, MENG-CHIEH WEN, LAN-HSIN CHIANG, LIN-TING LIN
  • Publication number: 20220261221
    Abstract: A random number generator and a random number generating method are provided. The random number generator includes a first stage generator and a second stage generator. The first stage generator outputs a first random number and a second random number at a first time point and a second time point, respectively. The second stage generator generates a final output at least according to the first random number. More particularly, the second stage generator includes a reseed circuit for generating a reseed signal, to control whether to generate the final output according to the second random number. In addition, when the second stage generator generates the final output at a current data cycle without using the second random number, the first stage generator holds the second random number for generating the final output at a next data cycle.
    Type: Application
    Filed: October 8, 2021
    Publication date: August 18, 2022
    Applicant: PUFsecurity Corporation
    Inventors: Chun-Heng You, Chi-Yi Shao, Kai-Hsin Chuang, Meng-Yi Wu
  • Patent number: 11402992
    Abstract: A control method applied to an electronic device with a first screen and a second screen is provided. The control method includes the following steps: receiving touch data responding to a touch behavior generated by the second screen; determining whether the touch behavior is a touchpad operation instruction or a touch screen operation instruction according to the touch data; triggering corresponding touchpad operation according to the touch data when the touch behavior is the touchpad operation instruction; and triggering corresponding touch screen operation according to the touch data when the touch behavior is the touch screen operation instruction.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: August 2, 2022
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chun-Tsai Yeh, Hung-Yi Lin, Meng-Ju Lu, Chien-Chih Tseng
  • Publication number: 20220238434
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire.
    Type: Application
    Filed: April 12, 2022
    Publication date: July 28, 2022
    Inventors: Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu
  • Publication number: 20220238523
    Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi PENG, Chun-Chieh LU, Meng-Hsuan HSIAO, Ling-Yen YEH, Carlos H. DIAZ, Tung-Ying LEE
  • Publication number: 20220217500
    Abstract: Provided in embodiments of the disclosure are methods, apparatuses, and computer-readable media for data processing. Location information and personalized information of a user are obtained in real-time; then a target spatial region corresponding to the location information is determined, the target spatial region including at least one physical object matching the personalized information; and then shopping guide data is generated for the user based on the at least one physical object matching the personalized information. By obtaining the real-time location of the user in combination with the personalized information of the user such as a purchase preference of historical purchase behavior, a shopping place and a branded shop near the user are provided to guide the user to perform in-store shopping, thereby improving purchase efficiency for the user, effectively providing personalized shopping recommended content to the user, and greatly improving purchase experience of the user.
    Type: Application
    Filed: December 3, 2021
    Publication date: July 7, 2022
    Inventors: Meng YI, Xu JIN, Ding JIANDONG