Patents by Inventor Meng Yi

Meng Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145381
    Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu
  • Patent number: 11959956
    Abstract: A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: April 16, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao
  • Publication number: 20240105136
    Abstract: An electronic device includes a display unit, a voltage generation unit, a grayscale adjustment unit, and an overdriving unit. The display unit has a relationship curve between the transmittance and the driving voltage. The relationship curve has a predetermined voltage value corresponding to the maximum transmittance. The voltage generation unit generates a first voltage according to a first grayscale, and generates a second voltage according to a second grayscale. The grayscale adjustment unit receives a first display grayscale value, and outputs the second grayscale value when the first display grayscale value is equal to the first grayscale. The overdriving unit overdrives the second voltage corresponding to the second grayscale to obtain a first target driving voltage, and it provides the first target driving voltage to the display unit.
    Type: Application
    Filed: August 17, 2023
    Publication date: March 28, 2024
    Inventors: Syue-Ling FU, Yeh-Yi LAN, Cheng-Cheng PAN, Meng-Kun TSAI
  • Patent number: 11940737
    Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Patent number: 11935890
    Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Chun-Chieh Lu, Meng-Hsuan Hsiao, Ling-Yen Yeh, Carlos H. Diaz, Tung-Ying Lee
  • Patent number: 11935841
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: March 19, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Meng-Wei Hsieh, Yu-Pin Tsai
  • Publication number: 20240081077
    Abstract: A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., National Yang Ming Chiao Tung University
    Inventors: Po-Tsun Liu, Meng-Han Lin, Zhen-Hao Li, Tsung-Che Chiang, Bo-Feng Young, Hsin-Yi Huang, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 11922855
    Abstract: An information handling system includes a host processing system and a Liquid Crystal Display device. The host processing system includes a graphics processing unit (GPU) and the LCD device includes a memory device and a DisplayPort Configuration Data (DPCD) register. The host processing system 1) determines whether the first GPU supports a Dynamic Display Shifting (DDS) mode, 2) when the GPU does not support the DDS mode, provides a first indication to the LCD device that the GPU does not support the DDS mode, and 3) when the GPU supports the DDS mode, provides a second indication to the LCD device that the GPU supports the DDS mode. The LCD device retrieves a Panel Self Refresh (PSR) setting from the memory device and stores the PSR setting to the DPCD register in response to the first indication, and retrieves a DDS setting from the memory and stores the DDS setting to the DPCD register in response to the second indication.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: March 5, 2024
    Assignee: Dell Products L.P.
    Inventors: Chun-Yi Chang, Yi-Fan Wang, Meng-Feng Hung, No-Hua Chuang, Yu Sheng Chang
  • Publication number: 20240072776
    Abstract: An entropy source circuit, comprising: a first adjustable ring oscillator for operating under a first setting or a second setting according to a first control signal, for respectively generating a first oscillation clock signal and a second oscillation clock signal which have different frequencies under the first setting and the second setting; a first sampling circuit, for sampling the first oscillating clock signal according to the sampling frequency to generate first sampling values, or sampling the second oscillating clock signal according to the sampling frequency to generate second sampling values; a first detection circuit detecting a first distribution of the first sampling values; and a control circuit generating the first control signal to switch the first setting to the second setting when the first distribution does not meet a predetermined distribution. The entropy source circuit outputs entropy values according to the first sample value or the second sample value.
    Type: Application
    Filed: July 6, 2023
    Publication date: February 29, 2024
    Applicant: PUFsecurity Corporation
    Inventors: Chi-Yi Shao, Kai-Hsin Chuang, Meng-Yi Wu
  • Publication number: 20240042096
    Abstract: The present invention provides an artificial dressing and a use of the artificial dressing for promoting wound healing. The artificial dressing includes a gelatin and a fungal extract.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 8, 2024
    Applicant: A.M.S. BioteQ Co., Ltd.
    Inventors: Yi-Ju Tsai, Ying-Ting Yeh, Meng-Yi Bai, Yun-Xuan Zhang
  • Patent number: 11876899
    Abstract: A random number generator includes a static random number generator, a dynamic entropy source, a counter and a combining circuit. The static random number generator includes an initial random number pool and a static random number pool to output a static random number sequence from one thereof the initial random number pool and the static random number pool. The dynamic entropy source is used to generate a dynamic entropy bit. The counter is used to generate a dynamic random number sequence according to the dynamic entropy bit. The combining circuit is used to output a true random number sequence to a lively random number pool according to the static random number sequence and the dynamic random number sequence. The static random number pool is updated when the lively random number pool is fully updated.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: January 16, 2024
    Assignee: PUFsecurity Corporation
    Inventors: Meng-Yi Wu, Chi-Yi Shao, Ching-Sung Yang
  • Publication number: 20230372577
    Abstract: Disclosures of the present invention describe a double-layer dressing containing silk fibroin and a method for making the same, wherein the double-layer dressing mainly comprises a silk fibroin layer and a calcium-degradation silk fibroin layer connected to the silk fibroin layer, and it is worth emphasizing that, results of animal experiment have proved that this novel double-layer dressing is an outstanding hemostatic wound dressing; Moreover, additional adhesion, resulted from the solidification of tissue fluid, can be effectively prevented from forming between skin wound and wound dressing under the use of this double-layer dressing.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 23, 2023
    Applicant: LIFE STAR INTERNATIONAL LIMITED
    Inventors: Meng-Yi BAI, Meng-Chuan Chen, Jia-Ying Lin, Wei-Yin Chen
  • Publication number: 20230333818
    Abstract: An entropy generator includes a physically unclonable function, a dynamic entropy source and an entropy enhancement engine. The physically unclonable function is used to provide a truly random static entropy. The dynamic entropy source is used to generate a dynamic entropy. The entropy enhancement engine is coupled to the physically unclonable function and the dynamic entropy source, and is used to generate an enhanced entropy according to the truly random static entropy and the dynamic entropy. The expected hamming distance is an expected value of a hamming distance between a truly random static entropy and another truly random static entropy provided by a physically unclonable function (PUF).
    Type: Application
    Filed: June 16, 2023
    Publication date: October 19, 2023
    Applicant: PUFsecurity Corporation
    Inventors: Meng-Yi Wu, Chi-Yi Shao, Ching-Sung Yang
  • Patent number: 11782090
    Abstract: A built-in self-test (BIST) circuit and a BIST method for Physical Unclonable Function (PUF) quality check are provided. The BIST circuit may include a PUF array, a readout circuit coupled to the PUF array, and a first comparing circuit coupled to the readout circuit. The PUF array may include a plurality of PUF units, wherein each of the PUF units includes a first cell and a second cell. The readout circuit may be configured to output an output bit from the first cell and output a parity bit from the second cell. The first comparing circuit may be configured to compare an output string with a parity string to generate a parity check result, wherein the output string includes output bits respectively read from selected PUF units of the PUF units, and the parity string includes parity bits read from the selected PUF units.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: October 10, 2023
    Assignee: PUFsecurity Corporation
    Inventors: Chi-Yi Shao, Kai-Hsin Chuang, Jun-Heng You, Meng-Yi Wu
  • Patent number: 11736286
    Abstract: A method and a secure boot control circuit for controlling a secure boot of an electronic device. The method is applicable to the secure boot control circuit, and the electronic device includes the secure boot control circuit. The method includes: checking randomness of an output of an entropy source of the secure boot control circuit to generate a check result; utilizing the entropy source to provide a random number sequence; generating a reference code according to the random number sequence; comparing the reference code with an activation code stored in the secure boot control circuit to generate a comparison result; and determining whether to enable at least one function of the electronic device according to at least one of the check result and the comparison result.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: August 22, 2023
    Assignee: PUFsecurity Corporation
    Inventors: Meng-Yi Wu, Chia-Cho Wu, Ching-Sung Yang
  • Publication number: 20230177173
    Abstract: An electronic device and a method for performing permission management of a storage device are provided. The storage device includes multiple storage blocks. The electronic device includes a controller and multiple dedicated interfaces, wherein the multiple dedicated interfaces are coupled to multiple ports of the controller. The controller is configured to perform access control of the storage device. The multiple dedicated interfaces correspond to the multiple storage blocks, and each dedicated interface of the multiple dedicated interfaces is configured to provide a dedicated channel for accessing one of the multiple storage blocks corresponding to said each dedicated interface via the controller.
    Type: Application
    Filed: October 6, 2022
    Publication date: June 8, 2023
    Applicant: PUFsecurity Corporation
    Inventors: Meng-Yi Wu, Chia-Cho Wu, Ching-Sung Yang
  • Publication number: 20220400966
    Abstract: A method for presenting data of blood-pressure measurement includes: calculating blood-pressure index values based on entries of data of blood-pressure measurement; and presenting a blood-pressure trend interface that includes index level regions, and for each of the blood-pressure index values, an index level markers disposed in one of the index level regions. The blood-pressure trend interface is presented in a manner that the index level markers corresponding respectively to the blood-pressure index values cooperatively indicate a trend in the blood pressure.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 22, 2022
    Inventor: Meng-Yi LIN
  • Patent number: 11446885
    Abstract: Disclosed is a friction-reducing and anti-wear composite material for a wading kinematic pair and a method of preparing the same. The friction-reducing and anti-wear composite material is prepared from carbon fiber (CF) among inorganic fillers, polyimide (PI) and polyether ether ketone (PEEK). These three materials are wet-mixed, dried and placed in a mold followed by curing by a heat press. The cured product is cooled and demolded to obtain the CF/PI/PEEK friction-reducing and anti-wear composite material for a wading kinematic pair. Tribological properties of the PEEK material are enhanced due to synergistic effect arising from hybrid organic-inorganic filling. The friction-reducing and anti-wear composite material provided in the invention has significantly reduced friction coefficient and wear volume loss under the seawater environment.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: September 20, 2022
    Assignee: Wuhan Research Institute Of Materials Protection
    Inventors: Haitao Duan, Tian Yang, Jian Li, Meng Yi, Jiesong Tu, Dan Jia, Shengpeng Zhan, Yongliang Jin, Jianwei Qi
  • Publication number: 20220261221
    Abstract: A random number generator and a random number generating method are provided. The random number generator includes a first stage generator and a second stage generator. The first stage generator outputs a first random number and a second random number at a first time point and a second time point, respectively. The second stage generator generates a final output at least according to the first random number. More particularly, the second stage generator includes a reseed circuit for generating a reseed signal, to control whether to generate the final output according to the second random number. In addition, when the second stage generator generates the final output at a current data cycle without using the second random number, the first stage generator holds the second random number for generating the final output at a next data cycle.
    Type: Application
    Filed: October 8, 2021
    Publication date: August 18, 2022
    Applicant: PUFsecurity Corporation
    Inventors: Chun-Heng You, Chi-Yi Shao, Kai-Hsin Chuang, Meng-Yi Wu
  • Publication number: 20220217500
    Abstract: Provided in embodiments of the disclosure are methods, apparatuses, and computer-readable media for data processing. Location information and personalized information of a user are obtained in real-time; then a target spatial region corresponding to the location information is determined, the target spatial region including at least one physical object matching the personalized information; and then shopping guide data is generated for the user based on the at least one physical object matching the personalized information. By obtaining the real-time location of the user in combination with the personalized information of the user such as a purchase preference of historical purchase behavior, a shopping place and a branded shop near the user are provided to guide the user to perform in-store shopping, thereby improving purchase efficiency for the user, effectively providing personalized shopping recommended content to the user, and greatly improving purchase experience of the user.
    Type: Application
    Filed: December 3, 2021
    Publication date: July 7, 2022
    Inventors: Meng YI, Xu JIN, Ding JIANDONG