Abstract: A servomotor type control system for a railroad track model includes a CPU, a key unit, and multiple servos; a player of the model achieves control operating status of those servos as desired by operating the key unit in conjunction with programming pre-installed in the CPU; accordingly, multiple point rails can be easily controlled and adjusted; the servo relates to a servomotor to allow rail switching highly imitating life situation as a breakthrough of conventional restriction to significantly upgrade delicate sense and precision of a railroad track model.

Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor comprising a substrate, a first conductive type MOS transistor, a second conductive type MOS transistor, a buffer layer, a first stress layer and a second stress layer is provided. The substrate has a device isolation structure therein that defines a first active area and a second active area. The first conductive type MOS transistor and the second conductive type MOS transistor are respectively disposed in the first active area and the second active area of the substrate. A first nitride spacer of the first conductive type MOS transistor has a thickness greater than that of a second nitride spacer of the second conductive type MOS transistor. The buffer layer is disposed on the first conductive type MOS transistor. The first stress layer is disposed on the buffer layer. The second stress layer is disposed on the second conductive type MOS transistor.

Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.

Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.

Abstract: A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.

Abstract: A method of fabricating a pixel structure is disclosed. A substrate having a color filter layer thereon and a leveling layer further covers the color filter layer is provided. A first metal layer is formed over the leveling layer. The first metal layer is patterned to define a source/drain. A channel material layer, a gate insulating layer and a second metal layer are formed over the substrate to cover the source/drain. The second metal layer, the gate insulating layer and the channel material layer are patterned to define a gate and a channel layer. A passivation layer is formed over the substrate to cover the gate. The passivation layer is patterned to expose a portion of the drain. A transparent conductive layer is formed over the substrate, and is electrically connected to the exposed drain. Thereafter, the transparent conductive layer is patterned to form a pixel electrode.

Abstract: The present invention discloses a management system and method for a biostrip. The management method is applicable to a biomedical measurement device to manage at least one biostrip. The management method comprises the following steps: inputting at least one piece of setting data of the biostrip; generating a count reference value based on the time of the inputted setting data, data content or combinations thereof; monitoring the expiration date of the biostrip corresponding to the count of the count reference value, and it further comprises displaying the current date, the expiration date of the biostrip, the amount of strips, the first opening date or combinations thereof. When the expiration date of the biostrip has passed, a user is then reminded to avoid using the expired biostrip.

Abstract: Transparent regions are allocated on the color filter regions to promote luminance of LCD devices. Shielding regions are allocated on the pixels regions of TFT substrate corresponding to the transparent regions to promote chromatics. These two designs can be adapted to both display devices for laptop computers with high luminance requirement and desktop computers with pure chromatics requirement.

Abstract: A display and a display panel thereof are provided. A driving circuit is formed on one side of the display panel to output an auxiliary scan signal to one terminal of the scan line in the display panel. A gate driver is formed on another side of the display panel to output a scan signal to another terminal of the scan line in the display panel, so that the two ends of a scan line in the display panel simultaneously receive the scan signal and the auxiliary scan signal. Thereby, not only the display quality of the display is improved and the difficult of repairing the display panel is reduced, but also the production yield rate of the display can be effectively increased. Besides, if the gate driver is not used in the display panel, the driving circuit can be simultaneously formed on both sides of the display panel.

Abstract: A liquid crystal display (LCD) panel with marks for checking cutting precision by visual inspection is provided. A checkerboard mark is formed on an intersection of two adjacent cutting lines of the LCD panel. The checkerboard mark includes a pair of first-square marks in a diagonal relationship and a pair of second-square marks in a diagonal relationship. When completing cutting of the LCD panel, the cutting precision of the LCD panel can be checked by visually inspecting the distance between the square mark and the cutting line or the residue of the checkerboard mark. The checkerboard mark is suitable for various LCD panels' arrangement.

Abstract: A method for manufacturing a lower substrate of a liquid crystal display device is disclosed. The method comprises the steps of: (a) forming a patterned first metal layer, a first insulating layer, a patterned second metal layer and a second insulating layer on a substrate in sequence; (b) coating a transparent electrode layer and a negative photo resist layer on the second insulating layer; (c) irradiating the photo resist layer from the second surface of the substrate; (d) irradiating the photo resist layer from the first surface of the substrate, wherein part of the photo resist layer superposed over the second metal layer is covered by a mask; and (e) removing un-reacted photo resist and patterning the transparent electrode.

Abstract: A liquid crystal display has a pixel array including first and second pixel electrodes. Each of the first pixel electrodes is divided into at least two first sub-pixel electrodes in two pixel areas sharing a corner or an edge. Similarly, each of the second pixel electrodes is divided into at least two second sub-pixel electrodes in two pixel areas sharing a corner or an edge. The polarities of the first and the second electrodes are opposite. The first and the second pixel electrodes are arranged alternatively to allow at least one first sub-pixel electrode and at least a second sub-pixel electrode to be located in each pixel area.

Abstract: Scan lines and data lines are disposed in a display region of a substrate, and multiple pixel regions are divided thereon. Switch components are disposed in the pixel regions, and each switch component is electrically connected to the scan line and data line. Pixel electrodes are disposed in the pixel regions and each pixel electrode is electrically connected to the switch component. Wires are disposed in a non-display region of the substrate, and at least one portion of each wire includes a first and a second conductor layer, wherein the second conductor layer is disposed on the first conductor layer and parallel-connected to the first conductor layer. The first conductor layer and one of the scan lines, data lines, and the pixel electrodes are in the same layer. The second conductor layer and another one of the scan lines, data lines, and the pixel electrodes are in the same layer.

Abstract: Pixel electrodes in a liquid crystal panel extend to cover the entire pixel regions. The light leakage is generated only on two sides of the pixel region due to the uncontinuous alignment of liquid crystal molecules when the liquid crystal panel is driven by dot inversion. Therefore, in the present invention, light-shielding layer is formed on only the corresponding region of the TFT substrate. The aperture ratio of the liquid crystal panel according to the present invention can increase and the light-shielding layer can be employed to repair the gate lines and data lines.

Abstract: A method of fabricating a pixel structure is disclosed. A substrate having a color filter layer thereon and a leveling layer further covers the color filter layer is provided. A first metal layer is formed over the leveling layer. The first metal layer is patterned to define a source/drain. A channel material layer, a gate insulating layer and a second metal layer are formed over the substrate to cover the source/drain. The second metal layer, the gate insulating layer and the channel material layer are patterned to define a gate and a channel layer. A passivation layer is formed over the substrate to cover the gate. The passivation layer is patterned to expose a portion of the drain. A transparent conductive layer is formed over the substrate, and is electrically connected to the exposed drain. Thereafter, the transparent conductive layer is patterned to form a pixel electrode.

Abstract: A method of fabricating a pixel structure is disclosed. A substrate having a color filter layer thereon and a leveling layer further covers the color filter layer is provided. A first metal layer is formed over the leveling layer. The first metal layer is patterned to define a source/drain. A channel material layer, a gate insulating layer and a second metal layer are formed over the substrate to cover the source/drain. The second metal layer, the gate insulating layer and the channel material layer are patterned to define a gate and a channel layer. A passivation layer is formed over the substrate to cover the gate. The passivation layer is patterned to expose a portion of the drain. A transparent conductive layer is formed over the substrate, and is electrically connected to the exposed drain. Thereafter, the transparent conductive layer is patterned to form a pixel electrode.

Abstract: A method of fabricating a pixel structure is disclosed. A substrate having a color filter layer thereon and a leveling layer further covers the color filter layer is provided. A first metal layer is formed over the leveling layer. The first metal layer is patterned to define a source/drain. A channel material layer, a gate insulating layer and a second metal layer are formed over the substrate to cover the source/drain. The second metal layer, the gate insulating layer and the channel material layer are patterned to define a gate and a channel layer. A passivation layer is formed over the substrate to cover the gate. The passivation layer is patterned to expose a portion of the drain. A transparent conductive layer is formed over the substrate, and is electrically connected to the exposed drain. Thereafter, the transparent conductive layer is patterned to form a pixel electrode.

Abstract: Transparent regions are allocated on the color filter regions to promote luminance of LCD devices. Shielding regions are allocated on the pixels regions of TFT substrate corresponding to the transparent regions to promote chromatics. These two designs can be adapted to both display devices for laptop computers with high luminance requirement and desktop computers with pure chromatics requirement.

Abstract: A method of fabricating a thin film transistor array is provided. A first patterned conductive layer that distributes over an area range exceeding the designated display region is formed over a substrate. A first dielectric layer is formed over the substrate, wherein the first dielectric layer has the thickness getting smaller toward the edge, so that the first patterned conductive layer outside the designated display region is exposed. A second patterned conductive layer is formed over the first dielectric layer. The second patterned conductive layer and the exposed first patterned conductive layer are electrically connected. A second dielectric layer having a plurality of contact openings therein is formed over the substrate. A plurality of pixel electrodes is formed over the second dielectric layer such that the pixel electrode and the second patterned conductive layer are electrically connected through the contact openings. Finally, various layers outside the designated display regions are removed.

Abstract: A wiring structure comprising a plurality of conductive wires coupled between a plurality of pixel terminals and a plurality of signal terminals of a flat panel display. Each conductive wire has a first portion of a first material with a first impedance and a second portion of a second material with a second impedance. Therefore, each conductive wire has the same impedance, thus enabling synchronous signal transmission and avoiding unstable display quality due to impedance disparity and asynchronous signals.