Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.

Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.

Abstract: A linear motion apparatus has a linear track, a slider and two sliding-assistant units for a linear motion apparatus. The sliding-assistant units for a linear motion apparatus is mounted between the track and the slider to enhance ease of movement between the track and the slider, and each sliding-assistant unit has two roller rings to receive rollers. The roller rings are elongated rectangular rings, are selectively mounted oppositely crossly around each other. Each roller ring is designed with reduced components to make manufacturing and assembling the sliding-assistant unit easier. Moreover, the roller ring is designed as one unity so no seam will be formed due to assembling two different pieces, such that ensures contact between the rollers and the roller ring smooth.

Abstract: A Secure Commerce and Asset/Supply Chain Management system and method provides displaying, commerce, asset management, global logistics, Customs declaration and recycling services for any user at anytime, anywhere with available communication network. Wireless sensors/identifier/computer/communicators, 2D graphic identifier, artificial intelligent and pervasive network communication/computing technologies are used to provide a user/friendly space. The user can interact with the system with mobile/wearable devices, or with movements/sounds made by his/her body. Embedded invisible sensing/computing/communication modules and/or holistic 3D virtual computing can be used to enhance user's experience. Major components of the system include an Intelligent Display Unit (IDU, 1), an Ubiquitous Information System (UIS, 2), a Secure Transport Unit (STU, 3), and a Personal Assistant Unit (PAU, 4).

Abstract: A method for manufacturing a lower substrate of a liquid crystal display device is disclosed. The method comprises the steps of: (a) forming a patterned first metal layer, a first insulating layer, a patterned second metal layer and a second insulating layer on a substrate in sequence; (b) coating a transparent electrode layer and a negative photo resist layer on the second insulating layer; (c) irradiating the photo resist layer from the second surface of the substrate; (d) irradiating the photo resist layer from the first surface of the substrate, wherein part of the photo resist layer superposed over the second metal layer is covered by a mask; and (e) removing un-reacted photo resist and patterning the transparent electrode.

Abstract: A method for manufacturing a lower substrate of a liquid crystal display device is disclosed. The method comprises the steps of: (a) forming a patterned first metal layer, a first insulating layer, a patterned second metal layer and a second insulating layer on a substrate in sequence; (b) coating a transparent electrode layer and a negative photo resist layer on the second insulating layer; (c) irradiating the photo resist layer from the second surface of the substrate; (d) irradiating the photo resist layer from the first surface of the substrate, wherein part of the photo resist layer superposed over the second metal layer is covered by a mask; and (e) removing un-reacted photo resist and patterning the transparent electrode.

Abstract: A liquid crystal display having dual data signal generation mechanism is disclosed for simplifying the display structure and retaining high display quality. The liquid crystal display includes a dual data signal generator, a preliminary data line, a first data line, a second data line, and a pixel unit. The dual data signal generator functions to convert a preliminary data signal, received from the preliminary data line, into a first data signal and a second data signal. The first and second data signals are furnished to the first and second data lines respectively. The pixel unit includes a first sub-pixel unit and a second sub-pixel unit. The first sub-pixel unit is coupled to the first data line for receiving the first data signal. The second sub-pixel unit is coupled to the second data line for receiving the second data signal.

Abstract: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.

Abstract: An inspecting device with an identification function is provided to identify and analyze different types of test specimens. (The test specimens include information to be measured and/or identification information.) In order to enable the inspecting device to identify the test specimen, an appropriate electrode pattern corresponding to an electrode in a specimen connection port of the inspecting device is arranged on one end of the test specimen. During a process of inserting the test specimen from an open end of the specimen connection port to reach a bottom end thereof, a logic change based on the electrode pattern detected by the connection port is utilized to identify the type of the specimen or read the information to be measured. A method for identifying different types of test specimens and a multifunctional test specimen is also provided.

Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.

Abstract: The present invention provides a biosensing device, comprising an input unit, an analysis unit, a process unit, and a set unit, to set up the calibration parameters of a strip in the device so that the calibration can be completed at a lower cost and be more user friendly.

Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device. The method includes at least the steps of forming a silicon germanium layer by the selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the selective growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Abstract: This present invention is a biological sensing meter and data communicating method thereof, applying an informative tag of the radio frequency identification technique to express the test item, the shelf expired date, the opening expired date, the sensing predetermined value, the number of test times as well as the test chip examination parameter and other calibration data under different test configurations. With the informative tag of the radio frequency identification technique, the test configuration can be set for testing different items, controlling the expired date of the test chip, and restoring test results of different test items.

Abstract: A linear motion apparatus has a linear track, a slider and two sliding-assistant units for a linear motion apparatus. The sliding-assistant units for a linear motion apparatus is mounted between the track and the slider to enhance ease of movement between the track and the slider, and each sliding-assistant unit has two roller rings to receive rollers. The roller rings are elongated rectangular rings, are selectively mounted oppositely crossly around each other. Each roller ring is designed with reduced components to make manufacturing and assembling the sliding-assistant unit easier. Moreover, the roller ring is designed as one unity so no seam will be formed due to assembling two different pieces, such that ensures contact between the rollers and the roller ring smooth.

Abstract: A semiconductor device includes a substrate defining an active area thereon, a shallow trench isolation on the substrate and directly surrounding the active area, a gate, a source and a drain on the active area and a hard mask on the border of the shallow trench isolation and the active area.

Abstract: A rolling element chain is applied to retain and arrange multiple rollers at intervals in a line and has a belt assembly and multiple clamping assemblies. The rollers are cylinders mounted parallelly in the rolling element chain. The belt assembly is resilient and has two parallel bars. The clamping assemblies are formed in pairs between the parallel bars to form multiple roller holes on the belt assembly and each clamping assembly has multiple clamping protrusions. The clamping protrusions of each clamping assembly are formed in a line between the parallel bars and alternately protrude oppositely away from the belt assembly and together hold the roller in the belt assembly. Each clamping protrusion has a roller surface and at least one rib. Each rib is formed on and protrudes from the roller surface, thereby, reduces contact area between the clamping protrusions and the rollers.

Abstract: A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap layer, a recess is formed through etching in the substrate. The patterned hard mask is removed after epitaxial layers are formed in the recesses. Accordingly, a conventional poly bump issue and an STI oxide loss issue leading to contact bridge can be avoided.

Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Abstract: A method for manufacturing a MOS transistor includes performing a thermal treatment to repair damaged substrate before forming source/drain extension regions, accordingly negative bias temperature instability (NBTI) is reduced. Since the thermal treatment is performed before forming the source/drain extension regions, heat budget for forming the source/drain extension regions and junction depth and junction profile of the source/drain extension would not be affected. Therefore the provided method for manufacturing a MOS transistor is capable of reducing short channel effect and possesses a superior process compatibility.

Abstract: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.