Patents by Inventor Meng-Yu Lin

Meng-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240103244
    Abstract: An anti-twist structure of voice coil motor includes a base, a lens housing, an elastic sheet, a magnet, and a yoke member. The lens housing has a margin wall, and the margin wall has a first protrusion and a contact portion. The elastic sheet has a hollowed slot, and the first protrusion pass through the hollowed slot, so that the elastic sheet is disposed on a portion of the margin wall and on the contact portion. The yoke member has an upper wall and a side wall. The side wall is disposed at one side of the upper wall and the side wall extends outward in a direction not parallel to the upper wall. The yoke member surrounds the lens housing, the elastic sheet, and the magnet. The lens housing has a deflectable angle relative to a horizontal reference line.
    Type: Application
    Filed: December 7, 2023
    Publication date: March 28, 2024
    Applicant: Lanto Electronic Limited
    Inventors: Wen-Yen Huang, Meng-Ting Lin, Fu-Yuan Wu, Shang-Yu Hsu, Bing-Bing Ma, Jie Du
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 11929331
    Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang, Chung-Hsing Wang
  • Publication number: 20240072115
    Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: February 13, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
  • Publication number: 20240072136
    Abstract: A semiconductor structure includes a first transistor, a second transistor, a metal rail, and a first source/drain contact and a second source/drain contact. The first transistor has a gate structure, a first source/drain feature, and a second source/drain feature. The first source/drain feature and the second source/drain feature are on opposite sides of the gate structure. The second transistor has the gate structure, a third source/drain feature directly over the first source/drain feature, and a fourth source/drain feature directly over the second source/drain feature. The metal rail extends in an X-direction and adjacent to the gate structure in a Y-direction. The first source/drain contact and the second source/drain contact each has an L-shape in a Y-Z cross-sectional view. The first source/drain contact electrically connects the first source/drain feature to the metal rail. The second source/drain contact electrically connects the fourth source/drain feature to the metal rail.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Yu LIN, Chun-Fu CHENG, Hsiang-Hung HUANG
  • Publication number: 20240014042
    Abstract: A semiconductor device includes a fin, first source/drain regions, second source/drain regions, a first nanosheet, a second nanosheet and a metal gate structure. The fin extends in a first direction and protrudes above an insulator. The first source/drain regions are over the fin. The second source/drain regions are over the first source/drain regions. The first nanosheet extends in the first direction between the first source/drain regions. The second nanosheet extends in the first direction between the second source/drain regions. The metal gate structure is over the fin and between the first source/drain regions. The metal gate structure extends in a second direction different from the first direction from a first sidewall to a second sidewall. A first distance in the second direction between the first nanosheet and the first sidewall is smaller than a second distance in the second direction between the first nanosheet and the second sidewall.
    Type: Application
    Filed: July 10, 2022
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Yu Lin, Chun-Fu Cheng, Cheng-Yin Wang, Yi-Bo Liao, Szuya Liao
  • Publication number: 20230317829
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a fin, and a semiconductor layer. The fin is over the substrate, the semiconductor layer is over the fin, the substrate and the fin are made of different materials, and the fin and the semiconductor layer are made of different materials. The method includes forming a dielectric layer over the semiconductor layer and the fin. The method includes forming a semiconductor structure over a sidewall of the dielectric layer. The method includes removing a first top portion of the dielectric layer over a top surface of the semiconductor layer. The method includes forming a gate over the semiconductor layer, the dielectric layer, and the semiconductor structure.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang WU, Kuo-An LIU, Kai Tak LAM, Meng-Yu LIN, Chun-Fu CHENG, Chieh-Chun CHIANG, Chun-Hsiang FAN
  • Publication number: 20230307456
    Abstract: An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor having a first semiconductor nanostructure corresponding to a channel region of the first semiconductor nanostructure and a first gate metal surrounding the second semiconductor nanostructure. The CFET includes a transistor including a second semiconductor nanostructure above the first semiconductor nanostructure and a second gate metal surrounding the second semiconductor nanostructure. The CFET includes an isolation structure between the first and second semiconductor nanostructures.
    Type: Application
    Filed: August 15, 2022
    Publication date: September 28, 2023
    Inventors: Meng-Yu LIN, Yi-Han WANG, Chun-Fu CHENG, Cheng-Yin WANG, Yi-Bo LIAO, Szuya LIAO
  • Publication number: 20230178603
    Abstract: Embodiments of the present disclosure relate to forming a nanosheet multi-channel device with an additional spacing layer and a hard mask layer. The additional spacing layer provides a space for an inner spacer above the topmost channel. The hard mask layer functions as an etch stop during metal gate etch back, providing improve gate height control.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 8, 2023
    Inventors: Shin-Jiun Kuang, Meng-Yu Lin, Chun-Fu Cheng, Chung-Wei WU
  • Patent number: 11569348
    Abstract: Embodiments of the present disclosure relate to forming a nanosheet multi-channel device with an additional spacing layer and a hard mask layer. The additional spacing layer provides a space for an inner spacer above the topmost channel. The hard mask layer functions as an etch stop during metal gate etch back, providing improve gate height control.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Jiun Kuang, Meng-Yu Lin, Chun-Fu Cheng, Chung-Wei Wu
  • Publication number: 20220278196
    Abstract: Embodiments of the present disclosure relate to forming a nanosheet multi-channel device with an additional spacing layer and a hard mask layer. The additional spacing layer provides a space for an inner spacer above the topmost channel. The hard mask layer functions as an etch stop during metal gate etch back, providing improve gate height control.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Shin-Jiun Kuang, Meng-Yu Lin, Chun-Fu Cheng, Chung-Wei WU
  • Publication number: 20220181202
    Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 9, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Yu LIN, Chun-Fu CHENG, Chung-Wei WU, Zhiqiang WU
  • Patent number: 11264270
    Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Yu Lin, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11171212
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Meng-Yu Lin, Shih-Yen Lin, Si-Chen Lee
  • Publication number: 20210125858
    Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.
    Type: Application
    Filed: March 19, 2020
    Publication date: April 29, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Meng-Yu LIN, Chun-Fu CHENG, Chung-Wei WU, Zhiqiang WU
  • Publication number: 20190319101
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.
    Type: Application
    Filed: April 22, 2019
    Publication date: October 17, 2019
    Inventors: Meng-Yu Lin, Shih-Yen Lin, Si-Chen Lee
  • Patent number: 10269902
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Yu Lin, Shih-Yen Lin, Si-Chen Lee
  • Patent number: 10157737
    Abstract: Semiconductor devices comprising two-dimensional (2D) materials and methods of manufacture thereof are described. In an embodiment, a method for manufacturing a semiconductor device comprising 2D materials may include: epitaxially forming a first 2D material layer on a substrate; and epitaxially forming a second 2D material layer over the first 2D material layer, the first 2D material layer and the second 2D material layer differing in composition.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: December 18, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Meng-Yu Lin, Shih-Yen Lin, Si-Chen Lee, Samuel C. Pan
  • Publication number: 20180122909
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 3, 2018
    Inventors: Meng-Yu LIN, Shih-Yen LIN, Si-Chen LEE
  • Publication number: 20180068851
    Abstract: Semiconductor devices comprising two-dimensional (2D) materials and methods of manufacture thereof are described. In an embodiment, a method for manufacturing a semiconductor device comprising 2D materials may include: epitaxially forming a first 2D material layer on a substrate; and epitaxially forming a second 2D material layer over the first 2D material layer, the first 2D material layer and the second 2D material layer differing in composition.
    Type: Application
    Filed: November 8, 2017
    Publication date: March 8, 2018
    Inventors: Meng-Yu Lin, Shih-Yen Lin, Si-Chen Lee, Samuel C. Pan