Abstract: A vertical-edge double-step sawtooth cutter for preparing high-quality holes of composite material and thereof hybrid stack structure, and has three parts which are a major cutting edge region A, a minor cutting edge region B and a shank region C. The minor cutting edge region B comprises a step vertical-edge region D and a sawtooth cutting region E. This has the step structure and the sawtooth structure which is distributed in the first step, has a recutting function at the inlet and a reverse cutting function at the outlet in the direction opposite to the main cutting motion. The cutter has the vertical edge structure distributed in the second step, and the angle of the second step is a negative value, thereby realizing chip breaking and crushing, reducing scratch to the upper-layer composite material and metal hole walls.

Abstract: A flexible display substrate, a method for manufacturing the same, a flexible display panel, and a flexible display device. The flexible display substrate includes: a flexible base substrate including a bendable region and an unbendable region, the bendable region including a bendable edge and an unbendable edge, the unbendable edge extending in a first direction; and at least one transistor in the bendable region of the flexible base substrate, including a gate electrode, a source region, a drain region, and an active layer, wherein the active layer extends in a direction substantially parallel to the first direction.

Abstract: The present application provides an anti-OX40 human antibody. In particular, a human antibody specifically binding to OX40 is obtained with yeast display screening, and the affinity of the antibody is improved with affinity maturation. The present application also provides a use of the antibody for the prevention or treatment of tumors.

Abstract: A display panel and a display device are provided. The display panel has a display area. The display panel includes: a base substrate; a driving circuit and at least one signal line on the base substrate; and at least one insulating layer between the driving circuit and the at least one signal line. The driving circuit is disposed in a periphery of the display area; and an orthogonal projection of at least one of the signal lines on the base substrate has an overlapping area with an orthogonal projection of the driving circuit on the base substrate.

Abstract: The present disclosure teaches semiconductor devices and methods for manufacturing the same. Implementations of the semiconductor device may include: a semiconductor substrate; a semiconductor fin positioned on the semiconductor substrate; and a gate structure positioned on the semiconductor fin, where the gate structure includes a gate dielectric layer on a part of a surface of the semiconductor fin and a gate on the gate dielectric layer; where the gate includes a metal gate layer on the gate dielectric layer and a semiconductor layer on a side surface of at least one side of the metal gate layer; and where the semiconductor layer includes a dopant, where a conductivity type of the dopant is the opposite of a conductivity type of the semiconductor fin. The present disclosure can improve a work function of the device, thereby improving a current characteristic of the device during a working process, reducing the short channel effect (SCE), and lowering a leakage current.

Abstract: The present disclosure provides proteinaceous complexes, pharmaceutical compositions, medicaments and/or kits comprising the proteinaceous complexes, methods for producing the proteinaceous complexes, and uses thereof.

Abstract: The present disclosure provides semiconductor devices and methods for manufacturing same and relates to the field of semiconductor technologies. Some implementations of a method may include: providing a semiconductor structure, where the semiconductor structure includes a substrate, a semiconductor fin having a first conductivity type and disposed on the substrate, and a gate structure covering a part of the semiconductor fin, where the semiconductor fin includes a first part and a second part respectively located on two sides of the gate structure; executing first doping on the first part and the second part of the semiconductor fin, where a dopant from the first doping has a second conductivity type that is opposite to the first conductivity type; and after the first doping is executed, forming a source on the first part of the semiconductor fin and forming a drain on the second part of the semiconductor fin.

Abstract: A method for fabricating an array substrate includes: forming a first metal layer on a base substrate; forming an insulating layer of a silicon-containing organic material on the first metal layer; forming a second metal layer on the insulating layer; patterning the second metal layer by adopting an oxygen ion etching process to partially cover the insulating layer; and forming a silicon oxide layer, by the oxygen ion etching process, on a surface of the insulating layer not covered by the second metal layer.

Abstract: The present disclosure teaches semiconductor devices and methods for manufacturing the same. Implementations of the semiconductor device may include: a semiconductor substrate; a semiconductor fin positioned on the semiconductor substrate; and a gate structure positioned on the semiconductor fin, where the gate structure includes a gate dielectric layer on a part of a surface of the semiconductor fin and a gate on the gate dielectric layer; where the gate includes a metal gate layer on the gate dielectric layer and a semiconductor layer on a side surface of at least one side of the metal gate layer; and where the semiconductor layer includes a dopant, where a conductivity type of the dopant is the opposite of a conductivity type of the semiconductor fin. The present disclosure can improve a work function of the device, thereby improving a current characteristic of the device during a working process, reducing the short channel effect (SCE), and lowering a leakage current.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a semiconductor substrate and a gate structure on the semiconductor substrate. The gate structure includes a gate dielectric layer on the semiconductor substrate, a gate on the gate dielectric layer, and a spacer layer on opposite sides of the gate. The method also includes etching the semiconductor substrate to form first and second recesses, etching a portion of the spacer layer to expose a surface portion of the semiconductor substrate, and forming a source filling the first recess and a drain filling the second recess. The source (drain) includes a first source (drain) portion in the first (second) recess and a second source (drain) portion on the first source (drain) portion. The second source portion or the second drain portion covers the exposed surface portion of the semiconductor substrate.

Abstract: The present disclosure provides PMOS transistors and fabrication methods thereof. An exemplary fabrication process of a PMOS transistor includes providing a semiconductor substrate having a surface; forming a gate structure on the surface of the semiconductor substrate; forming SiGe regions in the surface of the semiconductor substrate at two sides of the gate structure by implanting Ge ions into the semiconductor substrate; forming sidewalls on side surfaces of the gate structure and portions of surfaces of the SiGe regions close to the gate structure; removing portions of the SiGe regions at two sides of the gate structure to expose portions of the semiconductor substrate; forming trenches in the semiconductor substrate by etching the exposed portions of the semiconductor substrate at the two sides of the sidewalls; and forming source/drain regions by filling the trenches with a compressive stress material.

Abstract: The present disclosure provides proteinaceous heterodimers, pharmaceutical compositions, medicaments and/or kits comprising the proteinaceous heterodimers, methods for producing the proteinaceous heterodimers, and uses thereof.

Abstract: Disclosed are inhibitors of mevalonate pathway as an efficient vaccine adjuvant and use thereof. In particular, the inhibitor is an acetoacetyl-CoA transferase inhibitor, a HMG-CoA synthase inhibitor, a HMG-CoA reductase inhibitor, a mevalonate kinase inhibitor, a phosphomevalonate kinase inhibitor, a mevalonate-5-pyrophosphate decarboxylase inhibitor, an isopentenyl pyrophosphate isomerase inhibitor, a farnesyl pyrophosphate synthase inhibitor, a geranylgeranyl pyrophosphate synthase inhibitor or a geranylgeranyl transferase (I, II) inhibitor. Also disclosed is an immunogenic composition comprising inhibitors of mevalonate to pathway as an adjuvant.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a semiconductor substrate and a gate structure on the semiconductor substrate. The gate structure includes a gate dielectric layer on the semiconductor substrate, a gate on the gate dielectric layer, and a spacer layer on opposite sides of the gate. The method also includes etching the semiconductor substrate to form first and second recesses, etching a portion of the spacer layer to expose a surface portion of the semiconductor substrate, and forming a source filling the first recess and a drain filling the second recess. The source (drain) includes a first source (drain) portion in the first (second) recess and a second source (drain) portion on the first source (drain) portion. The second source portion or the second drain portion covers the exposed surface portion of the semiconductor substrate.

Abstract: A special end cutting edge attached cutter for carbon fiber reinforced polymer/plastic with designable micro-tooth configuration, having an end cutting edge, a peripheral cutting edge with variation inverse helical groove, a peripheral cutting edge with constant inverse helical groove and a shank. Two parallel V-shaped chip pockets are designed on the end cutting edge of the cutter in two cutting edge directions which are symmetrical around a cutter axis as a center. The structure may enhance chip removal performance during high-speed milling of impenetrable slots and impenetrable windows, reduce wear of the end cutting edge, conduct configuration design for micro-teeth of the peripheral cutting edge, reduce the cutting thickness of the micro-tooth cutting edges, and effectively solve the problem of damage of the micro-tooth edges. A section of peripheral cutting edge with variation left-hand inverse helical flute angle is designed near the end cutting edge.

Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a dummy gate structure over the base substrate; forming source/drain regions having source/drain doping ions in the base substrate at both sides of the dummy gate structure; forming a dielectric layer on the source/drain regions and covering the side surfaces of the dummy gate structure; removing the dummy gate structure to form an opening in the dielectric layer; performing one or more of a first ion implantation process, for implanting first barrier ions in the base substrate toward the source region to form a first barrier layer under the opening, and a second ion implantation process, for implanting second barrier ions in the base substrate toward the source region to form a second barrier layer under the opening; and forming a gate structure in the opening.

Abstract: The present disclosure provides semiconductor structures. An exemplary semiconductor structure includes a substrate having a first region and a second region; an isolation structure formed in the substrate in the first region; a compensation doping region formed in the substrate in the first region, locate at a side of the isolation structure adjacent to the substrate in the second region and connecting with the isolation structure; a well region formed in the substrate in the second region; a drift region formed in the substrate in the first region and enclosing the isolation structure and the compensation doping region; a gate structure formed over the substrate in a boundary region between the first region and the second region; a source region formed in the well region at one side of the gate structure; and a drain region formed in the drift region at another side of the gate structure.

Abstract: MOS transistors and fabrication methods are provided. An exemplary MOS transistor includes a gate structure formed on a semiconductor substrate. A lightly doped region is formed by a light ion implantation in the semiconductor substrate on both sides of the gate structure. A first halo region is formed by a first halo implantation to substantially cover the lightly doped region in the semiconductor substrate. A groove is formed in the semiconductor substrate on the both sides of the gate structure. Prior to forming a source and a drain in the groove, a second halo region is formed in the semiconductor substrate by a second halo implantation performed into a groove sidewall that is adjacent to the gate structure. The second halo region substantially covers the lightly doped region in the semiconductor substrate and substantially covers the groove sidewall that is adjacent to the gate structure.

Abstract: A display device includes a base substrate, a pixel defining layer, a spacer layer and a photosensitive circuit. The pixel defining layer is on the substrate and includes a pixel region and a pixel gap region; the spacer layer is on the pixel gap region of the pixel defining layer and at a side of the pixel defining layer away from the base substrate; and the photosensitive circuit is at a side of the pixel defining layer away from the spacer layer. The spacer layer is lightproof, a first opening is in the spacer layer, the first opening and the photosensitive circuit are overlapped with each other in a direction perpendicular to the base substrate, and the photosensitive circuit is configured to detect light passing through the first opening.

Abstract: The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a substrate having a first region and a second region; forming a trench in the substrate in the first region; forming a compensation doping region in a side surface of the trench adjacent to the second region; forming an isolation structure in the trench; forming a well region in the substrate in the second region; forming a drift region in the substrate in the first region; forming a gate structure over the substrate in a boundary region between the first region and the second region, and covering a portion of the isolation structure; and forming a source region in the well region at one side of the gate structure and a drain region in the drift region at another side of the gate structure.