Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate. Each sub-pixel includes a pixel circuit and pixel circuits are in columns in a first direction and rows in a second direction. The sub-pixels includes a first sub-pixel and a second sub-pixel which are directly adjacent in the second direction. A first capacitor electrode in the first sub-pixel and a first capacitor electrode in the second sub-pixel are in a same layer and are spaced apart from each other. The display substrate helps can reduce cross talk between signal lines so as to improve a display quality.

Abstract: Provided is a use of a mitoxantrone hydrochloride liposome in the preparation of a drug for treating urothelial cancer, breast cancer, and bone and soft tissue sarcoma. Further provided is a method for treating urothelial cancer, breast cancer, and bone and soft tissue sarcoma, and the method is to administer a therapeutically effective amount of mitoxantrone hydrochloride liposomes to a patient in need. The mitoxantrone hydrochloride liposome can effectively treat urothelial cancer, breast cancer, and bone and soft tissue sarcoma, and compared with common mitoxantrone hydrochloride injections, the mitoxantrone hydrochloride liposome has better therapeutic effect and fewer adverse reactions.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate. Each sub-pixel includes a pixel circuit and pixel circuits are in columns in a first direction and rows in a second direction. The sub-pixels includes a first sub-pixel and a second sub-pixel which are directly adjacent in the second direction. A first capacitor electrode in the first sub-pixel and a first capacitor electrode in the second sub-pixel are in a same layer and are spaced apart from each other.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, a pixel circuit layer and an anode layer; the pixel circuit layer includes a plurality of pixel driving circuits, the anode layer includes a plurality of anode groups, each of the plurality of anode groups includes a first anode and a second anode which are oppositely arranged, the first anode includes a first main body portion and a first connection portion, the first anode further includes an extension portion and an anode compensation portion, an orthographic projection of the anode compensation portion on the base substrate covers one thin film transistor in the pixel driving circuit connected to the first connection portion.

Abstract: Provided are a display panel and a display device. The display panel includes a base substrate as well as, at a side of the base substrate, a plurality of sub-pixels arranged in an array, a power bus, a plurality of first power lines extending along a column direction and a plurality of second power lines extending along a row direction, where each of the plurality of first power lines is electrically connected to the plurality of the sub-pixels arranged along the column direction, and the plurality of first power lines and the plurality of second power lines are electrically connected in overlapping regions of vertical projection on the base substrate. The display panel further includes a plurality of connection units.

Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes: a substrate; and a plurality of capacitor structures arranged on a surface of the substrate. Each of the plurality of capacitor structures extends in a first direction. The first direction is parallel to the surface of the substrate. Each of the plurality of capacitor structures includes a lower electrode layer, a capacitor dielectric layer and an upper electrode layer. The lower electrode layer is provided with a U-shaped groove. The U-shaped groove is at least completely filled with the capacitor dielectric layer and the upper electrode layer. The capacitor dielectric layer is arranged between the lower electrode layer and the upper electrode layer.

Abstract: A method for forming a semiconductor structure includes the following operations. A substrate is provided and includes a stacked structure and a first isolation structure that are alternately arranged in a first direction. A grid-like etched groove extending in the first direction is formed in the stacked structure and the first isolation structure, and divides the substrate into a first region and a second region that are arranged sequentially in a second direction. The first direction and the second direction are any two directions in a plane where the substrate is located. A second isolation structure is formed in the grid-like etched groove. A transistor structure and a capacitor structure are respectively formed in the first region and the second region, and are isolated by the second isolation structure.

Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes the following operations. A substrate is provided, includes a core region and a peripheral region. A preset barrier layer is formed on the substrate, and covers the core region and the peripheral region. At least a part of the preset barrier layer corresponding to the peripheral region is removed to expose a part of the substrate, and to take a reserved part of the preset barrier layer as a first barrier layer. A dielectric layer and a first conductive layer are successively formed on the first barrier layer and the substrate. A part of the dielectric layer and the first conductive layer on the first barrier layer are removed, to reserve a part of the dielectric layer and the first conductive layer on the first barrier layer closer to the peripheral region.

Abstract: A method for manufacturing a buried gate and a method for manufacturing a semiconductor device are disclosed. The method for manufacturing the buried gate includes that: a trench is provided on an active region of a substrate; a gate structure is filled in a bottom of the trench, and a trench sidewall above the gate structure is exposed; an epitaxial layer is grown on the exposed trench sidewall with an epitaxial growth process, in which the epitaxial layer does not close the trench; and an isolation layer is filled in the trench.

Abstract: The present disclosure provides a method of manufacturing a capacitor, a capacitor, and a memory, and relates to the technical field of semiconductors. The method of manufacturing a capacitor includes: providing a substrate; forming a first electrode on the substrate, the first electrode extending in a first direction parallel to the substrate, a size of the first electrode in the first direction being greater than a size of the first electrode in a second direction and a size of the first electrode in a third direction, and every two of the first direction, the second direction, and the third direction being perpendicular to each other; forming a dielectric layer wrapping the first electrode; and forming a second electrode wrapping the dielectric layer.

Abstract: A path planning method of mobile robots based on image processing is provided and includes: S1, preprocessing a map image: calculating a safety distance between a mobile robot and a surrounding obstacle during a movement of the mobile robot based on external geometric features of the mobile robot, forming a circular range on the map image with a expansion point as a center and the safety distance as an expansion radius to set a safety range, and marking the safety range; performing skeleton feature extraction on the map image after the marking to obtain a reference path map; S2, obtaining an initial path; and S3, optimizing the initial path. The path planning method improves the flexibility of the algorithm and has high robustness and operational efficiency, and the optimal path obtained can ensure the moving safety of the mobile robot.

Abstract: A path planning method of mobile robots based on image processing is provided and includes: S1, preprocessing a map image: calculating a safety distance between a mobile robot and a surrounding obstacle during a movement of the mobile robot based on external geometric features of the mobile robot, forming a circular range on the map image with a expansion point as a center and the safety distance as an expansion radius to set a safety range, and marking the safety range; performing skeleton feature extraction on the map image after the marking to obtain a reference path map; S2, obtaining an initial path; and S3, optimizing the initial path. The path planning method improves the flexibility of the algorithm and has high robustness and operational efficiency, and the optimal path obtained can ensure the moving safety of the mobile robot.

Abstract: A method for forming a capacitor includes: providing a substrate; sequentially forming a first sacrificial layer and a first support layer for covering the substrate; forming first openings penetrating through the first support layer; sequentially forming a second sacrificial layer and a second support layer for covering a remaining portion of the first support layer; forming through holes which sequentially penetrate through the second support layer, the second sacrificial layer, the remaining portion of the first support layer, and the first sacrificial layer; forming first electrode layers, each first electrode layer covering an inner wall of a respective one of the through holes; forming second openings penetrating through a remaining portion of the second support layer; and sequentially forming a dielectric layer and a second electrode layer for covering the first electrode layers, to form the capacitor.

Abstract: The present disclosure provides a photodiode based on a stannous selenide sulfide nanosheet/GaAs heterojunction and a preparation method and use thereof. The photodiode comprises a structure of the stannous selenide sulfide nanosheet/GaAs heterojunction, forming Au electrodes through thermal vapor deposition on the stannous selenide sulfide nanosheet and GaAs, respectively, and conducting an annealing treatment in a protective gas at a temperature in a range of 150-250° C. The heterojunction is formed by transferring the stannous selenide sulfide nanosheet to a GaAs window, and the GaAs window is obtained by depositing a medium layer film on GaAs and etching the medium layer through lithography and an etchant.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device and a semiconductor device. The method for manufacturing a semiconductor device includes: providing a substrate; forming a plurality of first structures extending in a first direction on the substrate; forming a sacrificial layer on sidewalls of the first structures; forming an outer spacer layer on a sidewall of the sacrificial layer; removing part of the outer spacer layer to obtain a patterned outer spacer layer that exposes part of the sacrificial layer; and removing the sacrificial layer to form air gaps between the patterned outer spacer layer and the first structures.

Abstract: A manufacturing method of a semiconductor structure includes the following operations. A substrate is provided, which includes a first N region, a first P region, a second N region and a second P region adjacently arranged in sequence. A gate dielectric layer, a first barrier layer, a first work function layer and a second barrier layer are formed on the substrate in sequence. A mask layer is formed on the second barrier layer of the first P region and the second P region. The second barrier layer of the first N region and the second N region is removed by a first etching process with the mask layer as a mask. The first work function layer and the first barrier layer of the first N region and the second N region are removed by a second etching process. A semiconductor structure is also provided.

Abstract: Embodiments relate to a semiconductor device and a forming method. The semiconductor device includes: a substrate; a memory array positioned on the substrate and at least including memory cells spaced along a first direction, each of the memory cells including a transistor, the transistor including a gate electrode, channel regions distributed on two opposite sides of the gate electrode along a third direction, and a source region and a drain region distributed on two opposite sides of each of the channel regions along a second direction, the first direction and the third direction being directions parallel to a top surface of the substrate, the first direction intersecting with the third direction, and the second direction being a direction perpendicular to the top surface of the substrate; and a word line extending along the first direction and continuously electrically connected to the gate electrodes spaced along the first direction.

Abstract: A memory and a method for preparing a memory are provided. The method for preparing the memory includes: providing a substrate, in which the substrate includes a first N-type active region and a first P-type active region; forming an epitaxial layer covering the first P-type active region, in which the epitaxial layer exposes the first N-type active region; simultaneously forming a first gate dielectric layer covering the first N-type active region and a second gate dielectric layer covering the epitaxial layer, in which a thickness of the first gate dielectric layer is substantially the same as a thickness of the second gate dielectric layer; forming a first gate covering the first gate dielectric layer to form a first N-channel Metal Oxide Semiconductor (NMOS) device; and forming a second gate covering the second gate dielectric layer to form a first P-channel Metal Oxide Semiconductor (PMOS) device.

Abstract: A memory includes a plurality of semiconductor structures stacked onto one another. Each of the plurality of semiconductor structures include: a first base including a peripheral circuit structure; a first integrated circuit layer disposed on the first base and electrically connected to the peripheral circuit structure; and a second base disposed on the first integrated circuit layer. A first dielectric layer is disposed between the first integrated circuit layer and the second base. The second base includes a storage circuit structure. Each of the first base and the second base includes a semiconductor layer.

Abstract: Provide is a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor memory. The method includes the following operations. A substrate is provided. Multiple silicon pillars are formed in the substrate, and extend along a first direction. In the first direction, each of the silicon pillars includes a first portion and a second portion. An insulating layer is formed in the second portion of the silicon pillar. A conductive layer is formed in the first portion of the silicon pillar. A capacitor layer is formed on surfaces of the insulating layer and the conductive layer of the silicon pillar.