Abstract: The invention can provide apparatus and methods of creating metal gate structures on wafers in real-time using Lithography-Etch-Lithography-Etch (LELE) processing sequence. Real-time data and/or historical data associated with LELE processing sequences can be fed forward and/or fed back as fixed variables or constrained variables in internal-Integrated-Metrology modules (i-IMM) to improve the accuracy of the metal gate structures.

Abstract: Method and system for producing a neutral beam source is described. The neutral beam source comprises a plasma generation system for forming a first plasma in a first plasma region, a plasma heating system for heating electrons from the first plasma region in a second plasma region to form a second plasma, and a neutralizer grid for neutralizing ion species from the second plasma in the second plasma region. Furthermore, the neutral beam source comprises a pumping system that enables use of the neutral beam source for semiconductor processing applications, such as etching processes.

Abstract: A plasma processing system includes a processing chamber, a substrate holder configured to hold a substrate for plasma processing, and a gas injection assembly. The gas injection assembly includes a first evacuation port located substantially in a center of the gas injection assembly and configured to evacuate gases from a central region of the substrate, and a gas injection system configured to inject gases in the process chamber. The plasma processing system also includes a second evacuation port configured to evacuate gases from a peripheral region surrounding the central region of the substrate.

Abstract: The invention can provide a method of processing a substrate using Spacer-Optimization (S-O) processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures. In addition, the S-O processing sequences can include one or more deposition procedures, one or more partial-etch procedures, one or more chemical oxide removal (COR)-etch procedures, one or more optimization procedures, one or more evaluation procedures, and/or one or more verification procedures.

Abstract: Method and system for producing a neutral beam source is described. The neutral beam source comprises a plasma generation system for forming a first plasma in a first plasma region, a plasma heating system for heating electrons from the first plasma region in a second plasma region to form a second plasma, and a neutralizer grid for neutralizing ion species from the second plasma in the second plasma region. Furthermore, the neutral beam source comprises an electron acceleration member configured to accelerate the electrons from the first plasma region into the second plasma region. Further yet, the neutral beam source comprises a pumping system that enables use of the neutral beam source for semiconductor processing applications, such as etching processes.

Abstract: A plasma processing system includes a processing chamber, a substrate holder configured to hold a substrate for plasma processing, and a gas injection assembly. The gas injection assembly includes a first evacuation port located substantially in a center of the gas injection assembly and configured to evacuate gases from a central region of the substrate, and a gas injection system configured to inject gases in the process chamber. The plasma processing system also includes a second evacuation port configured to evacuate gases from a peripheral region surrounding the central region of the substrate.

Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.

Abstract: The invention can provide apparatus and methods of processing a substrate in real-time using subsystems and processing sequences created to improve the etch resistance of photoresist materials. In addition, the improved photoresist layer can be used to more accurately control gate and/or spacer critical dimensions (CDs), to control gate and/or spacer CD uniformity, and to eliminate line edge roughness (LER) and line width roughness (LWR).

Abstract: A method and apparatus are provided to control the radial or non-radial temperature distribution across a substrate during processing to compensate for non-uniform effects, including radial and angular non-uniformities arising from system variations, or process variations, or both. The temperature is controlled, preferably dynamically, by flowing backside gas differently across different areas on a wafer supporting chuck to vary heat conduction across the wafer. Backside gas flow, of helium, for example, is dynamically varied across the chuck to control the uniformity of processing of the wafer. Ports in the support are grouped, and gas to or from the groups is separately controlled by different valves responsive to a controller that controls gas pressure in each of the areas to spatially and preferably dynamically control wafer temperature to compensate for system and process non-uniformities.

Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.

Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.

Abstract: The invention can provide a method of processing a wafer using a Real-Time Parameter Tuning (RTPT) procedure to receive an input message that can include a pass-through message, a real-time feedforward message, or a real-time optimization message, or any combination thereof. The RTPT procedures can use real-time wafer thickness data to create, modify, and/or use measurement recipe data, measurement profile data, and/or measurement model data. In addition, RTPT procedures can use real-time wafer thickness data to create, modify, and/or use process recipe data, process profile data, and/or process model data.

Abstract: Graphical User Interfaces (GUIs) are presented for configuring and setting-up dynamic sensors for monitoring tool and process performance in a semiconductor processing system. The semiconductor processing system includes a number of processing tools, a number of processing modules (chambers), and a number of sensors. The graphical display is organized so that all significant parameters are clearly and logically displayed so that the user is able to perform the desired configuration and setup tasks with as little input as possible. The GUI is web-based and is viewable by a user using a web browser.

Abstract: Method and system for producing a neutral beam source is described. The neutral beam source comprises a plasma generation system for forming a first plasma in a first plasma region, a plasma heating system for heating electrons from the first plasma region in a second plasma region to form a second plasma, and a neutralizer grid for neutralizing ion species from the second plasma in the second plasma region. Furthermore, the neutral beam source comprises an electron acceleration member configured to accelerate the electrons from the first plasma region into the second plasma region. Further yet, the neutral beam source comprises a pumping system that enables use of the neutral beam source for semiconductor processing applications, such as etching processes.

Abstract: A method of assessing damage of a dual damascene structure includes obtaining a wafer after the wafer has been processed using a dual damascene process. A first damage-assessment procedure is performed on the wafer using an optical metrology process to gather damage-assessment data for a first set of measurements sites on the wafer. For each measurement site in the first set of measurement sites, the optical metrology process determines an amount of damage of a damaged area of a periodic grating in the measurement site. The damage-assessment data includes the amount of damage determined by the optical metrology process. A first damage-assessment map is created for the dual damascene process. The first damage-assessment includes the damage-assessment data and the locations of the first set of measurement sites on the wafer. One or more values in the damage-assessment map are compared to damage-assessment limits established for the dual damascene process to identify the wafer as a damaged or undamaged wafer.

Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology includes directing an incident beam on the damaged structure. A diffracted beam is received from the damaged structure. The received diffracted beam is processed to determine a profile of an undamaged portion of the damaged structure and to measure an amount of dielectric damage of the damaged structure.

Abstract: The invention provides a method of processing a substrate using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more masking layer creation procedures, one or more pre-processing measurement procedures, one or more Partial-Etch (P-E) procedures, one or more Final-Etch (F-E) procedures, and one or more post-processing measurement procedures.

Abstract: A method is provided to cause deformation of a substrate during processing of the substrate.

Abstract: A method of creating a library for measuring a plurality of damaged structures formed on a semiconductor wafer using optical metrology includes directing an incident beam on a first damaged structure. The first damaged structure was formed by modifying at least one process parameter in a dual damascene procedure. A diffracted beam is received from the first damaged structure. A measured diffraction signal is obtained based on the received diffracted beam. A first simulated diffraction signal is calculated. The first simulated diffraction signal corresponds to a hypothetical profile of the first damaged structure. The hypothetical profile includes an undamaged dielectric portion and a damaged dielectric portion. The measured diffraction signal is compared to the first simulated diffraction signal.

Abstract: A method for facilitating an ODP (optical digital profile) measurement of a semiconductor wafer. The method includes obtaining real time wafer characteristic data for a measurement site on the wafer and detecting a measured diffraction signal from a structure within the measurement site of the wafer. The measured diffraction signal is matched with a simulated diffraction signal stored in a wafer characteristic dependent profile library. A hypothetical profile structure associated with the simulated diffraction signal in the wafer characteristic dependent profile library is then identified. The real time wafer characteristic data is used to facilitate at least one of the matching and identifying. The real time wafer characteristic data may be real time wafer thickness data.