Patents by Inventor Merritt Funk

Merritt Funk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080223873
    Abstract: A method and system for dynamically controlling a process chemistry above a substrate is described. The system for adjusting the process chemistry comprises a ring configured to surround a peripheral edge of a substrate in a vacuum processing system. The ring comprises one or more gas distribution passages formed within the ring and configured to supply an additive process gas through an upper surface of the ring to the peripheral region of the substrate, wherein the one or more gas distribution passages are configured to be coupled to one or more corresponding gas supply passages formed within the substrate holder upon which the ring rests.
    Type: Application
    Filed: March 12, 2007
    Publication date: September 18, 2008
    Applicant: Tokyo Electron Limited
    Inventors: Lee Chen, Radha Sundararajan, Merritt Funk
  • Publication number: 20080220340
    Abstract: Embodiments of an apparatus and methods for heating a substrate and a sacrificial layer are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: March 9, 2007
    Publication date: September 11, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: John Kulp, Michael A. Carcasi, Merritt Funk
  • Publication number: 20080183312
    Abstract: The invention can provide a method of etch processing a wafer using a Real-Time Parameter Tuning (RTPT) procedure to receive an input message that can include a pass-through message, a real-time feedforward message, or a real-time optimization message, or any combination thereof. The RTPT procedures can use real-time wafer data to create, modify, and/or use etch recipe data, etch profile data, and/or etch model data. In addition, RTPT procedures can use real-time wafer data to create, modify, and/or use process recipe data, process profile data, and/or process model data.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Merritt Funk, Sachin Deshpande, Kevin Lally
  • Publication number: 20080183412
    Abstract: The invention can provide a method of processing a wafer using a Real-Time Parameter Tuning (RTPT) procedure to receive an input message that can include a pass-through message, a real-time feedforward message, or a real-time optimization message, or any combination thereof. The RTPT procedures can use real-time wafer thickness data to create, modify, and/or use measurement recipe data, measurement profile data, and/or measurement model data. In addition, RTPT procedures can use real-time wafer thickness data to create, modify, and/or use process recipe data, process profile data, and/or process model data.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Merritt Funk, Sachin Deshpande, Kevin Lally
  • Publication number: 20080183411
    Abstract: A method for facilitating an ODP measurement of a semiconductor wafer. The method includes obtaining real time wafer characteristic data for a measurement site on said wafer and detecting a measured diffraction signal from a structure within the measurement site of the wafer. The measured diffraction signal is matched with a simulated diffraction signal stored in a wafer characteristic dependent profile library. A hypothetical profile structure associated with the simulated diffraction signal in the wafer characteristic dependent profile library is then identified. The real time wafer characteristic data is used to facilitate at least one of the matching and identifying. The real time wafer characteristic data may be real time wafer thickness data.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Merritt Funk, Sachin Deshpande, Kevin Lally
  • Publication number: 20080183413
    Abstract: A method for facilitating an ODP measurement of a semiconductor wafer. The method includes obtaining real time wafer characteristic data for a measurement site on said wafer and detecting a measured diffraction signal from a structure within the measurement site of the wafer. The measured diffraction signal is matched with a simulated diffraction signal stored in a wafer characteristic dependent profile library. A hypothetical profile structure associated with the simulated diffraction signal in the wafer characteristic dependent profile library is then identified. The real time wafer characteristic data is used to facilitate at least one of the matching and identifying.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Sachin Deshpande, Merritt Funk
  • Publication number: 20080182343
    Abstract: The invention can provide a method of processing a wafer using a Real-Time Parameter Tuning (RTPT) procedure to receive an input message that can include a pass-through message, a real-time feedforward message, or a real-time optimization message, or any combination thereof. The RTPT procedures can use real-time wafer temperature data to create, modify, and/or use measurement recipe data, measurement profile data, and/or measurement model data. In addition, RTPT procedures can use real-time wafer temperature data to create, modify, and/or use process recipe data, process profile data, and/or process model data.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Sachin Deshpande, Merritt Funk
  • Patent number: 7395131
    Abstract: A method for managing collected data in a semiconductor processing environment. The collected data can include: raw data collected during a process, trace file data received during a process, and process log file data received during a process. The raw data is synchronized with the trace file data and process log file data to create wafer data and summary data, and a file is created containing the wafer data and the summary data.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: July 1, 2008
    Assignee: Tokyo Electron Limited
    Inventor: Merritt Funk
  • Publication number: 20080137078
    Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology, the method includes obtaining a measured diffraction signal from a damaged periodic structure. A hypothetical profile of the damaged periodic structure is defined. The hypothetical profile having an undamaged portion, which corresponds to an undamaged area of a first material in the damaged periodic structure, and a damaged portion, which corresponds to a damaged area of the first material in the damaged periodic structure. The undamaged portion and the damaged portion have different properties associated with them. A simulated diffraction signal is calculated for the hypothetical damaged periodic structure using the hypothetical profile. The measured diffraction signal is compared to the simulated diffraction signal.
    Type: Application
    Filed: January 28, 2008
    Publication date: June 12, 2008
    Applicant: Tokyo Electron Limited
    Inventors: Kevin LALLY, Merritt FUNK, Radha SUNDARARAJAN
  • Patent number: 7328418
    Abstract: This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: February 5, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Asao Yamashita, Merritt Funk, Daniel Prager
  • Publication number: 20080027577
    Abstract: A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.
    Type: Application
    Filed: October 2, 2007
    Publication date: January 31, 2008
    Inventors: David Horak, Wesley Natzle, Merritt Funk, Kevin Lally, Daniel Prager
  • Patent number: 7324193
    Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology, the method includes obtaining a measured diffraction signal from a damaged periodic structure. A hypothetical profile of the damaged periodic structure is defined. The hypothetical profile having an undamaged portion, which corresponds to an undamaged area of a first material in the damaged periodic structure, and a damaged portion, which corresponds to a damaged area of the first material in the damaged periodic structure. The undamaged portion and the damaged portion have different properties associated with them. A simulated diffraction signal is calculated for the hypothetical damaged periodic structure using the hypothetical profile. The measured diffraction signal is compared to the simulated diffraction signal.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: January 29, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Kevin Lally, Merritt Funk, Radha Sundararajan
  • Patent number: 7305322
    Abstract: To determine the profile of an integrated circuit structure, a signal is measured off the structure with a metrology device. The measured signal is compared to signals in a virtual profile library. The comparison is stopped if matching criteria are met. A subset of a virtual profile data space is determined when the matching criteria are not met. The subset is determined using profile data space associated with the library. A virtual profile signal of the subset is selected. Virtual profile shape/parameters are determined based on the virtual profile signal. A difference is calculated between the measured and virtual profile signals. The difference is compared to virtual profile library creation criteria. If the criteria are met, then the structure is identified using virtual profile data, which includes the virtual profile shape/parameters, associated with the virtual profile signal. Or, if the criteria are not met, then a corrective action is applied.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: December 4, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Merritt Funk, Daniel Prager
  • Patent number: 7292906
    Abstract: A processing method of processing a substrate is presented that includes: receiving pre-process data, wherein the pre-process data comprises a desired process result and actual measured data for the substrate; determining a required process result, wherein the required process result comprises the difference between the desired process result and the actual measured data; creating a new process recipe by modifying a nominal recipe obtained from a processing tool using at least one of a static recipe and a formula model, wherein the new process recipe provides a new process result that is approximately equal to the required process result; and sending the new process recipe to the processing tool and the substrate.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: November 6, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Merritt Funk, Kevin Augustine Pinto, Asao Yamashita, Wesley Natzle
  • Publication number: 20070239383
    Abstract: A method of refining a virtual profile library includes obtaining a reference signal measured off a reference structure on a semiconductor wafer with a metrology device. A best match is selected of the reference signal in a virtual profile data space. The virtual profile data space has data points with specified accuracy values. The data points represent virtual profile parameters and associated virtual profile signals. The virtual profile parameters characterize the profile of an integrated circuit structure. The best match being a data point of the profile data space with a signal closest to the reference signal. Refined virtual profile parameters are determined corresponding to the reference signal based on the virtual profile parameters of the selected virtual profile signal using a refinement procedure.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 11, 2007
    Applicant: Tokyo Electron, Ltd.
    Inventors: Merritt Funk, Daniel Prager
  • Publication number: 20070238201
    Abstract: A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, bi-layer mask data, and BARC layer data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.
    Type: Application
    Filed: March 28, 2006
    Publication date: October 11, 2007
    Inventors: Merritt Funk, Radha Sundararajan, Daniel Prager, Wesley Natzle
  • Publication number: 20070239369
    Abstract: A method of creating a virtual profile library includes obtaining a reference signal. The reference signal was generated by measuring a signal off a reference structure on a semiconductor wafer with a metrology device. The reference signal is compared to a plurality of signals in a first library. The comparison is stopped if a first matching criteria is met. The reference signal is compared to a plurality of signals in a second library. The comparison is stopped if a second matching criteria is met. A virtual profile data space is created when the first and second matching criteria are not met. The virtual profile data space is created using differences between a profile data space associated with the first library and a profile data space associated with the second library. A first virtual profile signal is created in the virtual profile data space. A virtual profile shape and/or virtual profile parameters is created based on the first virtual profile signal.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 11, 2007
    Applicant: Tokyo Electron, Ltd.
    Inventors: Merritt Funk, Daniel Prager
  • Publication number: 20070237383
    Abstract: A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, or mask data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.
    Type: Application
    Filed: March 28, 2006
    Publication date: October 11, 2007
    Inventors: Merritt Funk, Radha Sundararajan, Daniel Prager, Wesley Natzle
  • Publication number: 20070233426
    Abstract: A method of using a virtual profile library to determine the profile of an integrated circuit structure includes measuring a signal off the structure with a metrology device. The measurement generates a measured signal. The measured signal is compared to a plurality of signals in at least one library. The comparison is stopped if a matching criteria is met. A subset of a virtual profile data space associated with the virtual profile library is determined when a matching criteria is not met. The subset is determined using profile data space associated with the at least one library. A virtual profile signal of the subset of the virtual profile data space is selected. A virtual profile shape and/or virtual profile parameters are determined based on the virtual profile signal. A difference is calculated between the measured signal and the virtual profile signal. The difference is compared to a virtual profile library creation criteria.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Applicant: Tokyo Electron, Ltd.
    Inventors: Merritt Funk, Daniel Prager
  • Publication number: 20070229807
    Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology, the method includes obtaining a measured diffraction signal from a damaged periodic structure. A hypothetical profile of the damaged periodic structure is defined. The hypothetical profile having an undamaged portion, which corresponds to an undamaged area of a first material in the damaged periodic structure, and a damaged portion, which corresponds to a damaged area of the first material in the damaged periodic structure. The undamaged portion and the damaged portion have different properties associated with them. A simulated diffraction signal is calculated for the hypothetical damaged periodic structure using the hypothetical profile. The measured diffraction signal is compared to the simulated diffraction signal.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 4, 2007
    Applicant: Tokyo Electron, Ltd.
    Inventors: Kevin Lally, Merritt Funk, Radha Sundararajan