Patents by Inventor Merritt Funk
Merritt Funk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080223873Abstract: A method and system for dynamically controlling a process chemistry above a substrate is described. The system for adjusting the process chemistry comprises a ring configured to surround a peripheral edge of a substrate in a vacuum processing system. The ring comprises one or more gas distribution passages formed within the ring and configured to supply an additive process gas through an upper surface of the ring to the peripheral region of the substrate, wherein the one or more gas distribution passages are configured to be coupled to one or more corresponding gas supply passages formed within the substrate holder upon which the ring rests.Type: ApplicationFiled: March 12, 2007Publication date: September 18, 2008Applicant: Tokyo Electron LimitedInventors: Lee Chen, Radha Sundararajan, Merritt Funk
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Publication number: 20080220340Abstract: Embodiments of an apparatus and methods for heating a substrate and a sacrificial layer are generally described herein. Other embodiments may be described and claimed.Type: ApplicationFiled: March 9, 2007Publication date: September 11, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: John Kulp, Michael A. Carcasi, Merritt Funk
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Publication number: 20080183312Abstract: The invention can provide a method of etch processing a wafer using a Real-Time Parameter Tuning (RTPT) procedure to receive an input message that can include a pass-through message, a real-time feedforward message, or a real-time optimization message, or any combination thereof. The RTPT procedures can use real-time wafer data to create, modify, and/or use etch recipe data, etch profile data, and/or etch model data. In addition, RTPT procedures can use real-time wafer data to create, modify, and/or use process recipe data, process profile data, and/or process model data.Type: ApplicationFiled: January 30, 2007Publication date: July 31, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Merritt Funk, Sachin Deshpande, Kevin Lally
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Publication number: 20080183412Abstract: The invention can provide a method of processing a wafer using a Real-Time Parameter Tuning (RTPT) procedure to receive an input message that can include a pass-through message, a real-time feedforward message, or a real-time optimization message, or any combination thereof. The RTPT procedures can use real-time wafer thickness data to create, modify, and/or use measurement recipe data, measurement profile data, and/or measurement model data. In addition, RTPT procedures can use real-time wafer thickness data to create, modify, and/or use process recipe data, process profile data, and/or process model data.Type: ApplicationFiled: January 30, 2007Publication date: July 31, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Merritt Funk, Sachin Deshpande, Kevin Lally
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Publication number: 20080183411Abstract: A method for facilitating an ODP measurement of a semiconductor wafer. The method includes obtaining real time wafer characteristic data for a measurement site on said wafer and detecting a measured diffraction signal from a structure within the measurement site of the wafer. The measured diffraction signal is matched with a simulated diffraction signal stored in a wafer characteristic dependent profile library. A hypothetical profile structure associated with the simulated diffraction signal in the wafer characteristic dependent profile library is then identified. The real time wafer characteristic data is used to facilitate at least one of the matching and identifying. The real time wafer characteristic data may be real time wafer thickness data.Type: ApplicationFiled: January 30, 2007Publication date: July 31, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Merritt Funk, Sachin Deshpande, Kevin Lally
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Publication number: 20080183413Abstract: A method for facilitating an ODP measurement of a semiconductor wafer. The method includes obtaining real time wafer characteristic data for a measurement site on said wafer and detecting a measured diffraction signal from a structure within the measurement site of the wafer. The measured diffraction signal is matched with a simulated diffraction signal stored in a wafer characteristic dependent profile library. A hypothetical profile structure associated with the simulated diffraction signal in the wafer characteristic dependent profile library is then identified. The real time wafer characteristic data is used to facilitate at least one of the matching and identifying.Type: ApplicationFiled: January 30, 2007Publication date: July 31, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Sachin Deshpande, Merritt Funk
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Publication number: 20080182343Abstract: The invention can provide a method of processing a wafer using a Real-Time Parameter Tuning (RTPT) procedure to receive an input message that can include a pass-through message, a real-time feedforward message, or a real-time optimization message, or any combination thereof. The RTPT procedures can use real-time wafer temperature data to create, modify, and/or use measurement recipe data, measurement profile data, and/or measurement model data. In addition, RTPT procedures can use real-time wafer temperature data to create, modify, and/or use process recipe data, process profile data, and/or process model data.Type: ApplicationFiled: January 30, 2007Publication date: July 31, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Sachin Deshpande, Merritt Funk
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Patent number: 7395131Abstract: A method for managing collected data in a semiconductor processing environment. The collected data can include: raw data collected during a process, trace file data received during a process, and process log file data received during a process. The raw data is synchronized with the trace file data and process log file data to create wafer data and summary data, and a file is created containing the wafer data and the summary data.Type: GrantFiled: February 15, 2005Date of Patent: July 1, 2008Assignee: Tokyo Electron LimitedInventor: Merritt Funk
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Publication number: 20080137078Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology, the method includes obtaining a measured diffraction signal from a damaged periodic structure. A hypothetical profile of the damaged periodic structure is defined. The hypothetical profile having an undamaged portion, which corresponds to an undamaged area of a first material in the damaged periodic structure, and a damaged portion, which corresponds to a damaged area of the first material in the damaged periodic structure. The undamaged portion and the damaged portion have different properties associated with them. A simulated diffraction signal is calculated for the hypothetical damaged periodic structure using the hypothetical profile. The measured diffraction signal is compared to the simulated diffraction signal.Type: ApplicationFiled: January 28, 2008Publication date: June 12, 2008Applicant: Tokyo Electron LimitedInventors: Kevin LALLY, Merritt FUNK, Radha SUNDARARAJAN
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Patent number: 7328418Abstract: This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.Type: GrantFiled: February 1, 2005Date of Patent: February 5, 2008Assignee: Tokyo Electron LimitedInventors: Asao Yamashita, Merritt Funk, Daniel Prager
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Publication number: 20080027577Abstract: A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.Type: ApplicationFiled: October 2, 2007Publication date: January 31, 2008Inventors: David Horak, Wesley Natzle, Merritt Funk, Kevin Lally, Daniel Prager
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Patent number: 7324193Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology, the method includes obtaining a measured diffraction signal from a damaged periodic structure. A hypothetical profile of the damaged periodic structure is defined. The hypothetical profile having an undamaged portion, which corresponds to an undamaged area of a first material in the damaged periodic structure, and a damaged portion, which corresponds to a damaged area of the first material in the damaged periodic structure. The undamaged portion and the damaged portion have different properties associated with them. A simulated diffraction signal is calculated for the hypothetical damaged periodic structure using the hypothetical profile. The measured diffraction signal is compared to the simulated diffraction signal.Type: GrantFiled: March 30, 2006Date of Patent: January 29, 2008Assignee: Tokyo Electron LimitedInventors: Kevin Lally, Merritt Funk, Radha Sundararajan
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Patent number: 7305322Abstract: To determine the profile of an integrated circuit structure, a signal is measured off the structure with a metrology device. The measured signal is compared to signals in a virtual profile library. The comparison is stopped if matching criteria are met. A subset of a virtual profile data space is determined when the matching criteria are not met. The subset is determined using profile data space associated with the library. A virtual profile signal of the subset is selected. Virtual profile shape/parameters are determined based on the virtual profile signal. A difference is calculated between the measured and virtual profile signals. The difference is compared to virtual profile library creation criteria. If the criteria are met, then the structure is identified using virtual profile data, which includes the virtual profile shape/parameters, associated with the virtual profile signal. Or, if the criteria are not met, then a corrective action is applied.Type: GrantFiled: March 31, 2006Date of Patent: December 4, 2007Assignee: Tokyo Electron LimitedInventors: Merritt Funk, Daniel Prager
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Patent number: 7292906Abstract: A processing method of processing a substrate is presented that includes: receiving pre-process data, wherein the pre-process data comprises a desired process result and actual measured data for the substrate; determining a required process result, wherein the required process result comprises the difference between the desired process result and the actual measured data; creating a new process recipe by modifying a nominal recipe obtained from a processing tool using at least one of a static recipe and a formula model, wherein the new process recipe provides a new process result that is approximately equal to the required process result; and sending the new process recipe to the processing tool and the substrate.Type: GrantFiled: July 14, 2004Date of Patent: November 6, 2007Assignee: Tokyo Electron LimitedInventors: Merritt Funk, Kevin Augustine Pinto, Asao Yamashita, Wesley Natzle
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Publication number: 20070239383Abstract: A method of refining a virtual profile library includes obtaining a reference signal measured off a reference structure on a semiconductor wafer with a metrology device. A best match is selected of the reference signal in a virtual profile data space. The virtual profile data space has data points with specified accuracy values. The data points represent virtual profile parameters and associated virtual profile signals. The virtual profile parameters characterize the profile of an integrated circuit structure. The best match being a data point of the profile data space with a signal closest to the reference signal. Refined virtual profile parameters are determined corresponding to the reference signal based on the virtual profile parameters of the selected virtual profile signal using a refinement procedure.Type: ApplicationFiled: March 31, 2006Publication date: October 11, 2007Applicant: Tokyo Electron, Ltd.Inventors: Merritt Funk, Daniel Prager
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Publication number: 20070238201Abstract: A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, bi-layer mask data, and BARC layer data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.Type: ApplicationFiled: March 28, 2006Publication date: October 11, 2007Inventors: Merritt Funk, Radha Sundararajan, Daniel Prager, Wesley Natzle
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Publication number: 20070239369Abstract: A method of creating a virtual profile library includes obtaining a reference signal. The reference signal was generated by measuring a signal off a reference structure on a semiconductor wafer with a metrology device. The reference signal is compared to a plurality of signals in a first library. The comparison is stopped if a first matching criteria is met. The reference signal is compared to a plurality of signals in a second library. The comparison is stopped if a second matching criteria is met. A virtual profile data space is created when the first and second matching criteria are not met. The virtual profile data space is created using differences between a profile data space associated with the first library and a profile data space associated with the second library. A first virtual profile signal is created in the virtual profile data space. A virtual profile shape and/or virtual profile parameters is created based on the first virtual profile signal.Type: ApplicationFiled: March 31, 2006Publication date: October 11, 2007Applicant: Tokyo Electron, Ltd.Inventors: Merritt Funk, Daniel Prager
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Publication number: 20070237383Abstract: A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, or mask data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.Type: ApplicationFiled: March 28, 2006Publication date: October 11, 2007Inventors: Merritt Funk, Radha Sundararajan, Daniel Prager, Wesley Natzle
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Publication number: 20070233426Abstract: A method of using a virtual profile library to determine the profile of an integrated circuit structure includes measuring a signal off the structure with a metrology device. The measurement generates a measured signal. The measured signal is compared to a plurality of signals in at least one library. The comparison is stopped if a matching criteria is met. A subset of a virtual profile data space associated with the virtual profile library is determined when a matching criteria is not met. The subset is determined using profile data space associated with the at least one library. A virtual profile signal of the subset of the virtual profile data space is selected. A virtual profile shape and/or virtual profile parameters are determined based on the virtual profile signal. A difference is calculated between the measured signal and the virtual profile signal. The difference is compared to a virtual profile library creation criteria.Type: ApplicationFiled: March 31, 2006Publication date: October 4, 2007Applicant: Tokyo Electron, Ltd.Inventors: Merritt Funk, Daniel Prager
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Publication number: 20070229807Abstract: A method of measuring a damaged structure formed on a semiconductor wafer using optical metrology, the method includes obtaining a measured diffraction signal from a damaged periodic structure. A hypothetical profile of the damaged periodic structure is defined. The hypothetical profile having an undamaged portion, which corresponds to an undamaged area of a first material in the damaged periodic structure, and a damaged portion, which corresponds to a damaged area of the first material in the damaged periodic structure. The undamaged portion and the damaged portion have different properties associated with them. A simulated diffraction signal is calculated for the hypothetical damaged periodic structure using the hypothetical profile. The measured diffraction signal is compared to the simulated diffraction signal.Type: ApplicationFiled: March 30, 2006Publication date: October 4, 2007Applicant: Tokyo Electron, Ltd.Inventors: Kevin Lally, Merritt Funk, Radha Sundararajan