Abstract: Provided are a modular multiplier apparatus in which a value of a long path carry (LPC) is predicted to reduce a critical path of an arithmetic operation of Montgomery modular multiplication, and a method of reducing the critical path of the arithmetic operation.

Abstract: Provided is a method of calculating a negative inverse of a modulus, wherein the negative inverse, which is an essential element in Montgomery multiplication, is quickly obtained. The method includes setting a modulus, defining P obtained by converting the modulus to a negative number, and defining S obtained by subtracting 1 from P, and calculating a negative inverse of the modulus by using P and S.

Abstract: A password system includes a user interface, a password generating unit, and a password checking unit. The password generating unit generates a password including multiple frames, generates an integrity check code associated with the generated password, and scrambles the generated password and provides the scrambled password to the user interface. The password checking unit stores the integrity check code, frame number information and scramble information which are provided from the password generating unit, descrambles a scrambled password that is input from the user interface based on the stored scramble information, and authenticates the user interface by comparing an integrity check code generated from the descrambled password and the stored integrity check code.

Abstract: In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.

Abstract: In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.

Abstract: Data cipher processors, advanced encryption standard (AES) cipher system, and AES cipher methods using a masking method perform round operations using a round key, a plain text, a cipher text, and masking data. Some of the round operations are implemented over a composite Galois Field GF(•). Original data and predetermined masking data are processed according to a predetermined rule. Sub-byte transformation operations used in the cipher method and system may include an affine transformation, an inverse affine transformation, an isomorphic transformation, and an inverse isomorphic transformation which are linear transformations, and an inverse transformation that is a non-linear transformation.

Abstract: Provided are a modular multiplier apparatus in which a value of a long path carry (LPC) is predicted to reduce a critical path of an arithmetic operation of Montgomery modular multiplication, and a method of reducing the critical path of the arithmetic operation.

Abstract: An apparatus, method and a computer program for processing multimedia data is described, where the apparatus may include an input switch which may receive a plurality of transport stream packets corresponding to a plurality of digital multimedia data signals input thereto, and a packet identification (PID) filter unit which may selectively output a given set of TS packets to be demultiplexed from the received plurality of TS packets. A buffer and/or an external memory device may store at least some of the TS packets of the output given set. A conditional access/content protection (CA/CP) unit may read and decrypt the TS packets stored in the buffer, and may encrypt at least some of the decrypted TS packets for storage in the external memory device if the buffer becomes full, to prevent the TS packets to be stored in the external memory device from being copied.

Abstract: A digital broadcast video receiving circuit includes a plurality of decoder circuits configured to decode an encoded digital broadcast video signal according to respective plurality of encoding formats to provide a digital data packet based on the encoded digital broadcast video signal. An encoding circuit is coupled to the plurality of decoder circuits and is configured to encode the digital data packet to provide a re-encoded digital data packet, related methods, and computer program products.

Abstract: In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.

Abstract: Provided is a method of calculating a negative inverse of a modulus, wherein the negative inverse, which is an essential element in Montgomery multiplication, is quickly obtained. The method includes setting a modulus, defining P obtained by converting the modulus to a negative number, and defining S obtained by subtracting 1 from P, and calculating a negative inverse of the modulus by using P and S.

Abstract: An engine, register in a memory, and methods for the same are provided. The engine may include a data encryptor, a key encryptor, a data decryptor, a key decryptor, a register, and a control circuit. The data encryptor may encrypt data using a key. The key encryptor may encrypt the key used by the data encryptor. The data decryptor may receive encrypted data from a storage medium and may decrypt the encrypted data. The key decryptor may receive an encrypted key from the storage medium and may decrypt the encrypted key. The register may indicate the status of the key and/or the encrypted key. The control circuit may control the data encryptor, the data decryptor, the key encryptor, the key decryptor, and the register.

Abstract: An M6 block cipher system and method for encoding content and authenticating a device may use an M6 core. The M6 block cipher system may include a rotate constant selector selecting one or more rotate constants from a plurality of input rotate constants for output based on a selection signal input thereto, a rotate constant ordering device ordering the selected rotate constants and a common rotate constant input thereto based on a received ordering signal and an M6 core generating one or more of an output signal, a validity signal and a round number based on the ordered rotate constants and a plurality of input signals. The system may include a rotate constant scheduler outputting the ordering signal to the rotate constant ordering device in response to the selection signal and the round number.

Abstract: A key scheduler, which may selectively generate an encryption round key and a decryption round key corresponding to an initial round key, which may have a variable key length. The key scheduler may include a key storage unit, a key calculating unit, and a key output unit. The key storage unit may receive and store calculation key data items or storage key data items as input key data items, and may output the stored input key data items as the storage key data items. The key calculating unit may output the calculation key data items as the calculation result. The key output unit may select units of the input key data items and the storage key data items in response to output control signals, and may output them as an encryption round key or a decryption round key.

Abstract: A password system includes a user interface, a password generating unit, and a password checking unit. The password generating unit generates a password including multiple frames, generates an integrity check code associated with the generated password, and scrambles the generated password and provides the scrambled password to the user interface. The password checking unit stores the integrity check code, frame number information and scramble information which are provided from the password generating unit, descrambles a scrambled password that is input from the user interface based on the stored scramble information, and authenticates the user interface by comparing an integrity check code generated from the descrambled password and the stored integrity check code.

Abstract: An M6 block cipher system and method for encoding content and authenticating a device may use an M6 core. The M6 block cipher system may include a rotate constant selector selecting one or more rotate constants from a plurality of input rotate constants for output based on a selection signal input thereto, a rotate constant ordering device ordering the selected rotate constants and a common rotate constant input thereto based on a received ordering signal and an M6 core generating one or more of an output signal, a validity signal and a round number based on the ordered rotate constants and a plurality of input signals. The system may include a rotate constant scheduler outputting the ordering signal to the rotate constant ordering device in response to the selection signal and the round number.

Abstract: Data cipher processors, advanced encryption standard (AES) cipher system, and AES cipher methods using a masking method perform round operations using a round key, a plain text, a cipher text, and masking data. Some of the round operations are implemented over a composite Galois Field GF(•). Original data and predetermined masking data are processed according to a predetermined rule. Sub-byte transformation operations used in the cipher method and system may include an affine transformation, an inverse affine transformation, an isomorphic transformation, and an inverse isomorphic transformation which are linear transformations, and an inverse transformation that is a non-linear transformation.

Abstract: An engine, register in a memory, and methods for the same are provided. The engine may include a data encryptor, a key encryptor, a data decryptor, a key decryptor, a register, and a control circuit. The data encryptor may encrypt data using a key. The key encryptor may encrypt the key used by the data encryptor. The data decryptor may receive encrypted data from a storage medium and may decrypt the encrypted data. The key decryptor may receive an encrypted key from the storage medium and may decrypt the encrypted key. The register may indicate the status of the key and/or the encrypted key. The control circuit may control the data encryptor, the data decryptor, the key encryptor, the key decryptor, and the register.

Abstract: A key scheduler, which may selectively generate an encryption round key and a decryption round key corresponding to an initial round key, which may have a variable key length. The key scheduler may include a key storage unit, a key calculating unit, and a key output unit. The key storage unit may receive and store calculation key data items or storage key data items as input key data items in response to load enable signals and a clock signal, and may output the stored input key data items as the storage key data items. The key calculating unit may calculate the storage key data items and may output the calculation key data items as the calculation result in response to calculation control signals. The key output unit may select units of the input key data items and the storage key data items in response to output control signals, and may output them as an encryption round key or a decryption round key.

Abstract: A hardware cryptographic engine implementing an Advanced Encryption Standard (AES) algorithm is disclosed. The hardware cryptographic engine comprises a plurality of modules corresponding to rounds of AES. Each of the plurality of modules comprises an S-BOX computing a multiplicative inverse of each element in an input vector over GF(28) using an operation over GF(((22)2)2), and replacing each element of the input vector with a substitute element obtained using a result of the operation.