Abstract: An M6 block cipher system and method for encoding content and authenticating a device may use an M6 core. The M6 block cipher system may include a rotate constant selector selecting one or more rotate constants from a plurality of input rotate constants for output based on a selection signal input thereto, a rotate constant ordering device ordering the selected rotate constants and a common rotate constant input thereto based on a received ordering signal and an M6 core generating one or more of an output signal, a validity signal and a round number based on the ordered rotate constants and a plurality of input signals. The system may include a rotate constant scheduler outputting the ordering signal to the rotate constant ordering device in response to the selection signal and the round number.

Abstract: Data cipher processors, advanced encryption standard (AES) cipher system, and AES cipher methods using a masking method perform round operations using a round key, a plain text, a cipher text, and masking data. Some of the round operations are implemented over a composite Galois Field GF(•). Original data and predetermined masking data are processed according to a predetermined rule. Sub-byte transformation operations used in the cipher method and system may include an affine transformation, an inverse affine transformation, an isomorphic transformation, and an inverse isomorphic transformation which are linear transformations, and an inverse transformation that is a non-linear transformation.

Abstract: A key scheduler, which may selectively generate an encryption round key and a decryption round key corresponding to an initial round key, which may have a variable key length. The key scheduler may include a key storage unit, a key calculating unit, and a key output unit. The key storage unit may receive and store calculation key data items or storage key data items as input key data items in response to load enable signals and a clock signal, and may output the stored input key data items as the storage key data items. The key calculating unit may calculate the storage key data items and may output the calculation key data items as the calculation result in response to calculation control signals. The key output unit may select units of the input key data items and the storage key data items in response to output control signals, and may output them as an encryption round key or a decryption round key.

Abstract: An engine, register in a memory, and methods for the same are provided. The engine may include a data encryptor, a key encryptor, a data decryptor, a key decryptor, a register, and a control circuit. The data encryptor may encrypt data using a key. The key encryptor may encrypt the key used by the data encryptor. The data decryptor may receive encrypted data from a storage medium and may decrypt the encrypted data. The key decryptor may receive an encrypted key from the storage medium and may decrypt the encrypted key. The register may indicate the status of the key and/or the encrypted key. The control circuit may control the data encryptor, the data decryptor, the key encryptor, the key decryptor, and the register.

Abstract: A hardware cryptographic engine implementing an Advanced Encryption Standard (AES) algorithm is disclosed. The hardware cryptographic engine comprises a plurality of modules corresponding to rounds of AES. Each of the plurality of modules comprises an S-BOX computing a multiplicative inverse of each element in an input vector over GF(28) using an operation over GF(((22)2)2), and replacing each element of the input vector with a substitute element obtained using a result of the operation.

Abstract: An apparatus, method and a computer program for processing multimedia data is described, where the apparatus may include an input switch which may receive a plurality of transport stream packets corresponding to a plurality of digital multimedia data signals input thereto, and a packet identification (PID) filter unit which may selectively output a given set of TS packets to be demultiplexed from the received plurality of TS packets. A buffer and/or an external memory device may store at least some of the TS packets of the output given set. A conditional access/content protection (CA/CP) unit may read and decrypt the TS packets stored in the buffer, and may encrypt at least some of the decrypted TS packets for storage in the external memory device if the buffer becomes full, to prevent the TS packets to be stored in the external memory device from being copied.

Abstract: A voice recognition device including dedicated arithmetic calculating modules for arithmetic operations that are more frequently required among arithmetic operations necessary for voice recognition, an observation probability calculating device for calculating probabilities that each of the phonemes of a pre-selected word can be observed upon voice recognition, a complex Fast Fourier Transform (FFT) calculation device and method of calculating a complex FFT of complex data, a cache, and a cache controlling method are provided. The arithmetic modules interpret commands received from a receiver and perform operations indicated by the commands.

Abstract: There is provided a semiconductor memory device and a method of pre-charging I/O lines therein. Multiplexers are controlled in such a way as to disconnect their normally connected switches only when desired, thereby reducing the number of pre-charging means employed as compared to prior art devices and methods.

Abstract: There is provided a semiconductor memory device and a method of pre-charging I/O lines therein. Multiplexers are controlled in such a way as to disconnect their normally connected switches only when desired, thereby reducing the number of pre-charging means employed as compared to prior art devices and methods.

Abstract: A merged semiconductor device having a DRAM and an SRAM, and a data transmitting method using the same are provided. In this device, the DRAM acts as a main memory, and the SRAM acts as a cache memory. The reading operation of the DRAM, and the writing operation of the SRAM are simultaneously controlled by a DRAM read control signal. Also, the writing operation of the DRAM, and the reading operation of the SRAM are simultaneously controlled by a DRAM write control signal. In this device, DRAM write commands and DRAM read commands can be continuously given. Writing of the SRAM starts after reading of the DRAM is completed, and writing of the DRAM starts after reading of the SRAM is completed.