Patents by Inventor Mi Ri Lee

Mi Ri Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180203418
    Abstract: An electronic device according to various embodiments of the present invention may comprise: a housing; a display device mounted on a surface of the housing; a bezel, which is rotatably coupled to the housing, and which rotates along the circumference of the display device; and elastic portions provided on the housing so as to provide the bezel with an elastic force in a first direction. The above electronic device may be implemented variously according to embodiments.
    Type: Application
    Filed: July 11, 2016
    Publication date: July 19, 2018
    Inventors: In-Sik CHUNG, Yong-Seok BANG, Mi-Ri LEE
  • Publication number: 20180175042
    Abstract: A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.
    Type: Application
    Filed: September 11, 2017
    Publication date: June 21, 2018
    Inventors: Il-Sik JANG, Ji-Hwan PARK, Mi-Ri LEE, Bong-Seok JEON, Yong-Soo JOUNG, Sun-Hwan HWANG
  • Patent number: 9850592
    Abstract: Provided is a method of forming a complex plating film using multi-layer graphene metal particles. The method of forming the plating film may include preparing a powder with a metal particle structure coated with multi-layer graphene, and forming a plating film by adding the powder to a plating solution through electric plating.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: December 26, 2017
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Su-Jeong Suh, Young-Il Song, Jung-Ho Park, Jung-Kab Park, Tae-Yoo Kim, Hwa-Jin Son, Jin-Ha Shin, Mi-Ri Lee, Jungwoo Lee, Changhyoung Lee, Younglae Cho, Seung-Bin Baeg, Byung-Wook Ahn, Sook-Young Yun
  • Patent number: 9728638
    Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 8, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jin-Ku Lee, Young-Ho Lee, Mi-Ri Lee
  • Patent number: 9418891
    Abstract: A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: August 16, 2016
    Assignee: SK Hynix Inc.
    Inventors: Kyong-Bong Rouh, Shang-Koon Na, Yong-Seok Eun, Su-Ho Kim, Tae-Han Kim, Mi-Ri Lee
  • Patent number: 9368586
    Abstract: A transistor including a recessed gate structure having improved doping characteristics and a method for forming such a transistor. The transistor includes a recess in a semiconductor substrate, where the recess is filled with a recessed gate structure including an impurity doped layer and a layer doped with a capture species. The capture species accumulates the impurity and diffuses the impurity to other layers of the recessed gate structure.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: June 14, 2016
    Assignee: SK Hynix Inc.
    Inventors: Kyong-Bong Rouh, Yong-Seok Eun, Mi-Ri Lee
  • Patent number: 9356005
    Abstract: Disclosed herein is a light emitting diode (LED) package. The present invention is directed to a light emitting diode (LED) package capable of efficiently dissipating heat generated from LEDs. The present invention is also directed to a LED package in which a plurality of LEDs are disposed and heat generated from the plurality of LEDs is efficiently dissipated.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: May 31, 2016
    Assignee: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Su-jeong Suh, Hwa-sun Park, Jung-kab Park, Tae-yoo Kim, Young-lae Cho, Mi-ri Lee, Jin-ha Shin, Hwa-jin Son, Jung-woo Lee
  • Publication number: 20160111535
    Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 21, 2016
    Inventors: Jin-Ku LEE, Young-Ho LEE, Mi-Ri LEE
  • Patent number: 9318390
    Abstract: A semiconductor device includes a semiconductor substrate and a gate insulation layer formed over the semiconductor substrate. A gate electrode is formed over the gate insulation layer. The gate electrode includes a silicon-containing electrode including a dopant, a capturing material to capture the dopant, and an activation control material to control an activation of the dopant.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: April 19, 2016
    Assignee: SK Hynix Inc.
    Inventors: Kyong-Bong Rouh, Shang-Koon Na, Mi-Ri Lee, Hun-Sung Lee
  • Publication number: 20160093527
    Abstract: A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer.
    Type: Application
    Filed: December 8, 2015
    Publication date: March 31, 2016
    Inventors: Kyong-Bong ROUH, Shang-Koon NA, Yong-Seok EUN, Su-Ho KIM, Tae-Han KIM, Mi-Ri LEE
  • Patent number: 9263575
    Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: February 16, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jin-Ku Lee, Young-Ho Lee, Mi-Ri Lee
  • Publication number: 20160024681
    Abstract: Provided is a method of forming a complex plating film using multi-layer graphene metal particles. The method of forming the plating film may include preparing a powder with a metal particle structure coated with multi-layer graphene, and forming a plating film by adding the powder to a plating solution through electric plating.
    Type: Application
    Filed: July 21, 2015
    Publication date: January 28, 2016
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Su-Jeong SUH, Young-Il SONG, Jung-Ho PARK, Jung-Kab PARK, Tae-Yoo KIM, Hwa-Jin SON, Jin-Ha SHIN, Mi-Ri LEE, Jungwoo LEE, Changhyoung LEE, Younglae CHO, Seung-Bin BAEG, Byung-Wook AHN, Sook-Young YUN
  • Patent number: 9236263
    Abstract: A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 12, 2016
    Assignee: SK Hynix Inc.
    Inventors: Kyong-Bong Rouh, Shang-Koon Na, Yong-Seok Eun, Su-Ho Kim, Tae-Han Kim, Mi-Ri Lee
  • Publication number: 20150348950
    Abstract: Disclosed herein is a light emitting diode (LED) package. The present invention is directed to a light emitting diode (LED) package capable of efficiently dissipating heat generated from LEDs. The present invention is also directed to a LED package in which a plurality of LEDs are disposed and heat generated from the plurality of LEDs is efficiently dissipated.
    Type: Application
    Filed: May 27, 2015
    Publication date: December 3, 2015
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Su-jeong SUH, Hwa-sun PARK, Jung-kab PARK, Tae-yoo KIM, Young-lae CHO, Mi-ri LEE, Jin-ha SHIN, Hwa-jin SON, Jung-woo LEE
  • Patent number: 9076864
    Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: July 7, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jin-Ku Lee, Young-Ho Lee, Mi-Ri Lee
  • Patent number: 9054128
    Abstract: A doping method that forms a doped region at a desired location of a three-dimensional (3D) conductive structure, controls the doping depth and doping dose of the doped region relatively easily, has a shallow doping depth, and prevents a floating body effect. A semiconductor device is fabricated using the same doping method. The method includes, forming a conductive structure having a sidewall, exposing a portion of the sidewall of the conductive structure, and forming a doped region in the exposed portion of the sidewall by performing a plasma doping process.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: June 9, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jin-Ku Lee, Jae-Geun Oh, Young-Ho Lee, Mi-Ri Lee, Seung-Beom Baek
  • Publication number: 20150155207
    Abstract: A semiconductor device includes a semiconductor substrate and a gate insulation layer formed over the semiconductor substrate. A gate electrode is formed over the gate insulation layer. The gate electrode includes a silicon-containing electrode including a dopant, a capturing material to capture the dopant, and an activation control material to control an activation of the dopant.
    Type: Application
    Filed: February 10, 2015
    Publication date: June 4, 2015
    Inventors: Kyong-Bong ROUH, Shang-Koon NA, Mi-Ri LEE, Hun-Sung LEE
  • Patent number: 8981486
    Abstract: A semiconductor device includes a semiconductor substrate and a gate insulation layer formed over the semiconductor substrate. A gate electrode is formed over the gate insulation layer. The gate electrode includes a silicon-containing electrode including a dopant, a capturing material to capture the dopant, and an activation control material to control an activation of the dopant.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 17, 2015
    Assignee: SK Hynix Inc.
    Inventors: Kyong-Bong Rouh, Shang-Koon Na, Mi-Ri Lee, Hun-Sung Lee
  • Patent number: D831605
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Ho Baik, Mi-Ri Lee, Jong-Bo Jung, Seon-Keun Park
  • Patent number: D839250
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Ho Baik, Mi-Ri Lee, Jong-Bo Jung, Seon-Keun Park