Abstract: A method of removing the residue left after a plasma process is described. First, a substrate having at least a material layer thereon is provided. The material layer includes a metal. Then, a fluorine-containing plasma process is performed so that a residue containing the aforesaid metallic material is formed on the surface of the material layer. After that, a wet cleaning operation is performed using a cleaning agent to remove the residue. The cleaning agent is a solution containing water, a diluted hydrofluoric acid and an acid solution.

Abstract: A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.

Abstract: A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.

Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

Abstract: A method of removing the residue left after a plasma process is described. First, a substrate having at least a material layer thereon is provided. The material layer includes a metal. Then, a fluorine-containing plasma process is performed so that a residue containing the aforesaid metallic material is formed on the surface of the material layer. After that, a wet cleaning operation is performed using a cleaning agent to remove the residue. The cleaning agent is a solution containing water, a diluted hydrofluoric acid and an acid solution.

Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues.

Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

Abstract: A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.

Abstract: A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.

Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A first wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues. A second wet treatment is performed to completely remove the residues.

Abstract: A dual damascene structure comprising a substrate, a dielectric layer, a metal hard mask layer, a protection layer and a conductive layer is provided. The substrate has a conductive area. The dielectric layer is disposed on the substrate. The metal hard mask layer is disposed on the dielectric layer. The protection layer is disposed on the metal hard mask layer. A trench is disposed in the protection layer, the metal hard mask layer and a part of the dielectric layer. An opening is disposed in the dielectric layer under the trench. The opening exposes the conductive area. The conductive layer is disposed in the trench and the opening.

Abstract: A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.

Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A first wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues. A second wet treatment is performed to completely remove the residues.