Abstract: Generation of documentation from a computer readable symbolic representation is described. In an embodiment, a reified version of an input is obtained as coded objects. The input is readable by a programmed computer for execution, and is in an applied form of a symbolic representation of knowledge for a defined domain of knowledge. The reified version is a coded form of the applied form, wherein the coded objects are in a dynamic language. A content sequence library is accessed by the programmed computer responsive to the coded objects to extract content for a document plan. A reasoning library is then accessed by the programmed computer responsive to the content extracted to provide a sequenced organization of phrase structure for the content extracted. A natural language representation of the input is output from a realization of the sequenced organization of phrase structure.

Abstract: A method is provided for generating a hardware description language (HDL) specification of a network packet processor from a textual language specification of the processing of network packets by the processor. The processor includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The textual language specification identifies the ports of the processor. The textual language specification includes formats for the type or types of the incoming and outgoing network packets. Each format includes the fields of the type of network packet. The textual language specification includes a procedure for each input port and for each type of incoming network packet received at the input port. Each procedure includes one or more actions for modifying the fields of a type of network packet as a function of state data and/or the fields of the type of network packet.

Abstract: In-system signal monitoring using an integrated circuit such as a programmable logic device is described. An analog-to-digital converter is disposed in the programmable logic device. A sampling bridge is coupled to provide an analog input to the analog-to-digital converter and to receive first signaling of a first frequency. A signal generator is configured to provide second signaling at a second frequency which is a fraction of the first frequency. Sample window circuitry is coupled to receive the second signaling and configured to provide third signaling to the sampling bridge at least partially responsive to the second signaling and at least partially responsive to an adjustable impedance setting of the sample window circuitry. The sample window circuitry is configured to provide an adjustable sample window within a pulse-width range.

Abstract: Data-processing systems including processor datapaths that efficiently support computationally advantageous routing operations are disclosed. Data-processing methods based on such systems are also disclosed. An exemplary data-processing system includes a register file, a routing unit, a switch, and an arithmetic logic unit. The arithmetic logic unit may include a bitwise function unit, pipeline register, and an accumulator. The switch may have N data inputs and logM(N) switching stages. M may equal 2 or 4. In the case of log2(N) stages, each switching stage has N/2 switching cells. The routing unit may include a control logic that generates a control signal, and various logics that respectively operate on various bit groups of the control signal.

Abstract: A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an suction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA).

Abstract: Method for in-system signal analysis is described. A programmable logic device is coupled within a signal communications system. A signal processing core is instantiated in programmable logic of the programmable logic device. At least one communication signal is provided to the programmable logic device, where the at least one communication signal has a first frequency. The at least one communication signal is sampled at a second frequency which is less than the first frequency to obtain samples thereof. The samples are converted from analog signals to digital signals. The digital signals are analyzed with at least in part the signal processing core.

Abstract: Data-processing systems including processor datapaths that efficiently support computationally advantageous routing operations are disclosed. Data-processing methods based on such systems are also disclosed. An exemplary data-processing system includes a register file, a routing unit, a Banyan switch, and an arithmetic logic unit. The arithmetic logic unit may include a bitwise function unit, pipeline register, and an accumulator. The Banyan switch may have N data inputs and logM(N) switching stages. M may equal 2 or 4. In the case of log2(N) stages, each switching stage has N/2 switching cells. The routing unit may include a control logic that generates a control signal, and various logics that respectively operate on various bit groups of the control signal.

Abstract: A reduced instruction set computer architecture implemented on a field programmable gate array includes a parallel bit shifter capable of reversible shifts and bit reversals, a Reed-Muller Boolean unit coupled to the parallel bit shifter and an immediate instruction function using a half-word literal field in an instruction word that impacts a whole word logically through a combination of modes that variously manipulates the distribution of a set of literal bits of the half-word literal field across the instruction word.

Abstract: A system (20) for dynamic reconfigurable computing includes at least one microprocessor implemented on a field programmable gate array (10) having a programmable fabric (12). The system can include a predefined interface (42) between an embedded microprocessor and the programmable fabric as well as a translator (25) enabling a single hardware description language to define the system including both the microprocessor and the programmable fabric.

Abstract: A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA).

Abstract: A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA).

Abstract: An apparatus for performing phase-lock in a field programmable gate array includes a phase detector configured to determine a phase difference between a carry logic oscillator signal and a reference clock signal; and a combinational circuit coupled to the phase detector, and adapted to function as a variable carry logic oscillator, and further configured to generate the carry logic oscillator signal. A method for performing phase-lock in a field programmable gate array includes: using a carry logic oscillator in a field programmable gate array to generate a carry logic oscillator signal; and determining a phase difference between the carry logic oscillator signal and a reference clock signal.

Abstract: A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA).

Abstract: A data-processing system comprises a register file, a routing unit, a Banyan switch, a switch control unit, a constant generator, and an arithmetic logic unit. The arithmetic logic unit comprises a bitwise function unit, pipeline register, and an accumulator. The Banyan switch may have an internal bitwidth of w and comprise N switching stages. N may equal log2(w) or log4(w). In the case of log2(w) stages, each switching stage has N/2 switching cells. The routing unit comprises a control logic that generates a control signal, and various logics that respectively operate on various bit groups of the control signal. The switch control unit comprises a shift constants generator, a pipeline flip-flop, and a switch tree. A data-processing method implemented by the above system is also disclosed.

Abstract: A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA).

Abstract: A compiling system and method generates a sequence of program instructions for use in a partially reconfigurable processing unit, a portion of the processing unit having a hardware organization that is selectively reconfigurable during execution of the sequence of program instructions among a plurality of configurations, and a portion of the processing unit having a non-reconfigurable hardware organization, each configuration comprising a computational unit optimized for performing a class of computations. A compiler selectively compiles high-level source code statements for execution using configurations of the reconfigurable portion of the processing unit responsive to meta-syntax compiler directives. A linker creates object files that optionally encapsulate bitstreams specifying hardware organizations corresponding to the configurations.

Abstract: A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA).

Abstract: An automatic capture device, situated between a telephone line and a fax machine, provides real-time monitoring, recording, and selective modification of fax transmissions, and forwarding of the fax data to a computer interface. The automatic capture device is dynamically reconfigurable, capable of adaptation to a variety of facsimile formats and computer interfaces.

Abstract: A compiling system and method for generating a sequence of program instructions for use in a dynamically reconfigurable processing unit having an internal hardware organization that is selectively changeable among a plurality of hardware architectures, each hardware architecture executing instructions from a corresponding instruction set. Source files are compiled for execution using various instruction set architectures as specified by reconfiguration directives. Object files optionally encapsulate bitstreams specifying hardware architectures corresponding to instruction set architectures with executable code for execution on the architectures.

Abstract: An apparatus for self-timed algorithmic execution comprises a functional logic set, a reference clock input and a pulse sequencer. The functional logic set receives input data in synchrony with a reference pulse set received at the reference clock input; performs algorithmic computations on the input data at a maximal-rate set by the pulse sequencer in accordance with the physical characteristics of the functional logic; generates output data; and transmits the output data in synchrony with the reference pulse set. The maximal-rate set by the pulse sequencer is independent of the reference pulse set.