Abstract: A master time-base unit generates quadrature-phase sinusoidal system reference signals that are phase-locked to a frequency reference oscillator. Based upon messaging signals received from an external source, each system reference signals is modulated according to direct carrier amplitude modulation, and is distributed to local time-base units via a transmission line. Within each local time-base unit, local reference signals and an offset signal are generated, where the local reference signals are phase-locked to the modulated system reference signals. A local reference signal and the offset signal are mixed to generate a local timing signal via frequency upconversion. A frequency-divided version of the local timing signal is phase-locked to a frequency-divided version of a local reference signal. Reprogrammable frequency dividers in combination with phase-lock facilitate the programmable specification of local timing signal frequencies.

Abstract: A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA).

Abstract: A polycyclic timing system and an apparatus for pipelined computer operation comprises a master state machine and a slave state machine. The master state marine produces a plurality of control signals in response to a clock signal. The master state machine comprises an oscillator, a plurality of data storage elements, and a next state feedback network. The oscillator is used to produce a clock signal that triggers the storage elements. The next state feedback network determines the control signals to output based on the current output data storage elements using logic in the next state feedback network. The slave state machine receives the control signals and uses them to produce several asynchronous pulse streams. The slave state machine preferably comprises a plurality of pulse forming state machines and a plurality of pulse transmission amplifiers.

Abstract: A polycyclic timing system and an apparatus for pipelined computer operation comprises a master state machine and a slave state machine. The master state machine produces a plurality of control signals in response to a clock signal. The master state machine comprises an oscillator, a plurality of data storage elements, and a next state feedback network. The oscillator is used to produce a clock signal that triggers the storage elements. The next state feedback network determines the control signals to output based on the current output data storage elements using logic in the next state feedback network. The slave state machine receives the control signals and uses them to produce several asynchronous pulse streams. The slave state machine preferably comprises a plurality of pulse forming state machines and a plurality of pulse transmission amplifiers.

Abstract: A minimal instruction set computer architecture (hyperscalar computer architecture) comprises a central memory, an instruction buffer, a control unit, an I/O control unit, a plurality of functional units, a plurality of register files, and a data router. In the hyperscalar computer architecture, the central memory transfers a plurality of instructions to the instruction buffer. The control unit receives multiple instructions from the instruction buffer, and automatically determines and issues the largest subset of instructions from those received that can be simultaneously issued to the plurality of functional units. Each functional unit receives data from and returns computational results to a corresponding register file. The data router serves to transfer data between each register file and any other register file, the central memory, the control unit, or the I/O control unit.

Abstract: This invention provides an instruction-driven, bit stream sequencer for digital computers that uses a reduced instruction set with as few as four instructions. The sequencer receives a sequence of M-bit control words; and each control word consists of an m.sub.1 -bit flag select word that selects an input or output line (out of a population of up to 2.sup.m.sbsp.1 lines) and an m.sub.2 -bit op code word that selects from among a population of 2.sup.m.sbsp.2 instructions, with m.sub.1 +m.sub.2 =M. The sequencer uses two one-bit registers and a logic function unit. One register receives a bit from the input port of the sequencer and passes the bit to the logic function unit. The second register, which holds a bit representing the present state of the processing, also passes this bit to the logic function unit for formation of a logical function or command based on these two bits; the second register also serves as the source of bits for the output lines of the sequencer.

Abstract: An architecture for bistable circuits with minimized sensitivity to metastability events and with improved operation in signal timing, arbitration, and protocol applications. Conventional edge-triggered flip-flops require input signals to remain present during certain set-up and/or hold time intervals on an input line "data path" for sampling at an instant determined by a separate synchronization input signal. In contrast, the present invention uses two edge-sensitive input lines which are triggered essentially independently without either being synchronized by or depending upon the other. The flip-flops also have twin, independently operable, level sensitive and selected priority PRESET and CLEAR input lines. The active edge or level polarity is programmable for each input line. Alternate embodiments for complementary classes of asynchronous timing perform specific bistable functions, such as set-reset, or toggle.