Abstract: An optical recording medium, comprises a substrate, an imaging composition disposed on said substrate, said compound comprising: a matrix, a color-forming agent, and a nucleating agent. The nucleating agent increases the nucleation density of at least one component of the color-forming agent.

Abstract: A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A system and method for limiting the size of a local storage of a processor are provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: A system and method for communicating instructions and data between a processor and external devices are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A system and method for asynchronously traversing a disjoint linked data structure is presented. A synergistic processing unit (SPU) includes a handler that works in conjunction with a memory flow controller (MFC) to traverse a disjoint linked data structure. The handler compares a search value with a node value, and provides the MFC with an effective address of the next node to traverse based upon the comparison. In turn, the MFC retrieves the corresponding node data from system memory and stores the node data in the SPU's local storage area. The MFC stalls processing and sends an asynchronous event interrupt to the SPU which, as a result, instructs the handler to retrieve and compare the latest node data in the local storage area with the search value. The traversal continues until the handler matches the search value with a node value or until the handler determines a failed search.

Abstract: The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.

Abstract: Various embodiments of a method, coating and system for conductive patterning are disclosed.

Abstract: A dense ceramic electrolyte membrane supported by symmetrical porous ceramic electrolyte layers. The thin (t<100 microns) electrolyte layer is sandwiched between two fugitive-containing electrolyte support layers that become highly porous after firing. The heat treated fugitive-containing support layers form a skeletal structure of strongly adhered electrolyte with an interpenetrating network of pores that extends well always from the electrolyte surface. The porous layers can be infiltrated with a range of electrode materials or precursors to form a solid oxide fuel cell or other electrochemical cell as well as electrochemical cell stacks. The supported ceramic membrane provides electrochemical performance advantages and reduces warpage during sintering compared to conventional structures.

Abstract: The present invention provides several improvements in a slip ring (36) that is adapted to provide electrical contact between a rotor (42) and stator (40). In one aspect, a brush tube (39) is crimped around the upper marginal end portions of a plurality of individual fibers (38) inserted therein. In another aspect, a collimator tube (41) extends downwardly beyond the end of the brush tube to limit lateral movement of the fibers in the bundle when the rotor rotates. In yet another arrangement, a spring (55, 56) is arranged to bear against a current-carrying conductor to adjustably vary the force by which the lower ends of the fibers are urged to move toward the rotor.

Abstract: Methods and apparatus provide for logically-partitioning respective processors of a multi-processing system into a plurality of resource groups; and time-allocating resources among the resource groups as a function of a predetermined algorithm.

Abstract: A memory module according to one implementation includes a support substrate, plural memory devices mounted on the support substrate, and pins having a predetermined arrangement on the support substrate, the pins comprising signal pins connected to the memory devices, power pins, and ground pins. In the predetermined arrangement of pins, each signal pin uses a ground pin as a reference, and each power pin is adjacent a ground pin for reduced impedance between the power pin and ground pin. In some implementations, some of the signal pins are associated with redundant pins.

Abstract: Self-supporting thin film membranes of ceramic materials and related electrochemical cells and cell stacks. The membrane structure is divided into a plurality of self-supporting thin membrane regions by a network of thicker integrated support ribs. The membrane structure may be prepared by laminating a thin electrolyte layer with a thicker ceramic layer that forms a network of support ribs.

Abstract: The intensity of specularly reflected light from an illuminated object is represented by an algebraic expression including multiplication, addition, and subtraction operations. The algebraic expression is used in an illumination model, where the illumination model describes the color and intensity of light reflected by the illuminated object. Light reflected by the illuminated object is composed of ambient, diffuse, and specular components. The specular terms used in the illumination model are equivalent in functional form to the diffuse terms, thereby accelerating the computation of color vector c defined by the illumination model. A modified algebraic expression representing specularly reflected light from an illuminated object is defined and used in the illumination model, thereby accelerating computation of color vector c.

Abstract: Systems and methods for the efficient utilization of threads in a processor with multiple execution paths are disclosed. These systems and methods alleviate the need to perform context switching in one or more threads while simultaneously allowing these threads to run useful tasks. One or more of these threads may run tasks in a privileged mode, thus there may be no need to save and restore context in these threads. Additionally, by keeping the threads executing in privileged mode at a lower priority, these privileged mode tasks can run exclusively on one or more of these threads without significantly delaying the execution of other threads.

Abstract: Embodiments of memory modules and corresponding methods are disclosed. One memory module embodiment includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second addressing register each having at least one of address and control input routing primarily provided in a first layer, the first addressing register coupled to the upper row of memory integrated circuits and the second addressing register coupled to the lower row of memory integrated circuits.

Abstract: An improved Extensible Style Language Transformations (XSLT) processor adapts to dynamic environmental conditions of a target platform on which the XSLT processor operates. Based on the dynamic environment condition(s) of the target platform, the XSLT processor, using an Extensible Markup Language—Remote Procedure Calling (XML-RPC) source document and an Extensible Style Language (XSL) stylesheet, generates customized script that accomplishes the directive of the XML-RPC source document.

Abstract: The invention disclosed relates to cross-linkable composites of boronic acid or a boronic acid derivative such as a boronate, and an organic or organo-metallic moiety having a functionality such as hole transporting, electron transporting and light emitting, to cross-linked composites and to methods for making same. Multi-layer materials and optoelectronic devices including such cross-linked composites are also disclosed.

Abstract: Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the shared memory and the DMAC is operatively coupled to the local memory.

Abstract: A markable material includes a base matrix material, a thermally activated marking material, and at least one colorant.

Abstract: The present invention provides a method of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. In an embodiment of the invention, a processor can write data to the cache or other fast memory without also writing it to main memory. The portion of the cache or other fast memory can be used as additional system memory.