Abstract: FinFET devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided having an active layer on an insulator. A plurality of fin hardmasks are patterned on the active layer. A dummy gate is placed over a central portion of the fin hardmasks. One or more doping agents are implanted into source and drain regions of the device. A dielectric filler layer is deposited around the dummy gate. The dummy gate is removed to form a trench in the dielectric filler layer. The fin hardmasks are used to etch a plurality of fins in the active layer within the trench. The doping agents are activated. A replacement gate is formed in the trench, wherein the step of activating the doping agents is performed before the step of forming the replacement gate.

Abstract: A method of fabricating a FET device is provided that includes the following steps. A wafer is provided. At least one active area is formed in the wafer. A plurality of dummy gates is formed over the active area. Spaces between the dummy gates are filled with a dielectric gap fill material such that one or more keyholes are formed in the dielectric gap fill material between the dummy gates. The dummy gates are removed to reveal a plurality of gate canyons in the dielectric gap fill material. A mask is formed that divides at least one of the gate canyons, blocks off one or more of the keyholes and leaves one or more of the keyholes un-blocked. At least one gate stack material is deposited onto the wafer filling the gate canyons and the un-blocked keyholes. A FET device is also provided.

Abstract: Techniques for integrating low temperature salicide formation in a replacement gate device process flow are provided. In one aspect, a method of fabricating a FET device is provided that includes the following steps. A dummy gate(s) is formed over an active area of a wafer. A gap filler material is deposited around the dummy gate. The dummy gate is removed selective to the gap filler material, forming a trench in the gap filler material. A replacement gate is formed in the trench in the gap filler material. The replacement gate is recessed below a surface of the gap filler material. A gate cap is formed in the recess above the replacement gate. The gap filler material is etched back to expose at least a portion of the source and drain regions of the device. A salicide is formed on source and drain regions of the device.

Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.

Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.

Abstract: A MEMS transistor for a FBEOL level of a CMOS integrated circuit is disclosed. The MEMS transistor includes a cavity within the integrated circuit. A MEMS cantilever switch having two ends is disposed within the cavity and anchored at least at one of the two ends. A gate and a drain are in a sidewall of the cavity, and are separated from the MEMS cantilever switch by a gap. In response to a voltage applied to the gate, the MEMS cantilever switch moves across the gap in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit into electrical contact with the drain to permit a current to flow between the source and the drain. Methods for fabricating the MEMS transistor are also disclosed. In accordance with the methods, a MEMS cantilever switch, a gate, and a drain are constructed on a far back end of line (FBEOL) level of a CMOS integrated circuit in a plane parallel to the FBEOL level.

Abstract: A stack of an organic planarization layer (OPL) and a template layer is provided over a substrate. The template layer is patterned to induce self-assembly of a copolymer layer to be subsequently deposited. A copolymer layer is deposited and annealed to form phase-separated copolymer blocks. An original self-assembly pattern is formed by removal of a second phase separated polymer relative to a first phase separated polymer. The original pattern is transferred into the OPL by an anisotropic etch, and the first phase separated polymer and the template layer are removed. A spin-on dielectric (SOD) material layer is deposited over the patterned OPL that includes the original pattern to form SOD portions that fill trenches within the patterned OPL. The patterned OPL is removed selective to the SOD portions, which include a complementary pattern. The complementary pattern of the SOD portions is transferred into underlying layers by an anisotropic etch.

Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nano gap.

Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap.

Abstract: A stack of a hard mask layer, a soft mask layer, and a photoresist is formed on a substrate. The photoresist is patterned to include at least one opening. The pattern is transferred into the soft mask layer by an anisotropic etch, which forms a carbon-rich polymer that includes more carbon than fluorine. The carbon-rich polymer can be formed by employing a fluorohydrocarbon-containing plasma generated with fluorohydrocarbon molecules including more hydrogen than fluorine. The carbon-rich polymer coats the sidewalls of the soft mask layer, and prevents widening of the pattern transferred into the soft mask. The photoresist is subsequently removed, and the pattern in the soft mask layer is transferred into the hard mask layer. Sidewalls of the hard mask layer are coated with the carbon-rich polymer to prevent widening of the pattern transferred into the hard mask.

Abstract: A SIT method includes the following steps. An SIT mandrel material is deposited onto a substrate and formed into a plurality of SIT mandrels. A spacer material is conformally deposited onto the substrate covering a top and sides of each of the SIT mandrels. Atomic Layer Deposition (ALD) is used to deposit the SIT spacer at low temperatures. The spacer material is selected from the group including a metal, a metal oxide, a metal nitride and combinations including at least one of the foregoing materials. The spacer material is removed from all but the sides of each of the SIT mandrels to form SIT sidewall spacers on the sides of each of the SIT mandrels. The SIT mandrels are removed selective to the SIT sidewall spacers revealing a pattern of the SIT sidewall spacers. The pattern of the SIT sidewall spacers is transferred to the underlying stack or substrate.

Abstract: A stack of an organic planarization layer (OPL) and a template layer is provided over a substrate. The template layer is patterned to induce self-assembly of a copolymer layer to be subsequently deposited. A copolymer layer is deposited and annealed to form phase-separated copolymer blocks. An original self-assembly pattern is formed by removal of a second phase separated polymer relative to a first phase separated polymer. The original pattern is transferred into the OPL by an anisotropic etch, and the first phase separated polymer and the template layer are removed. A spin-on dielectric (SOD) material layer is deposited over the patterned OPL that includes the original pattern to form SOD portions that fill trenches within the patterned OPL. The patterned OPL is removed selective to the SOD portions, which include a complementary pattern. The complementary pattern of the SOD portions is transferred into underlying layers by an anisotropic etch.

Abstract: A silicidation blocking process is provided. In one aspect, a silicidation method is provided. The method includes the following steps. A wafer is provided having a semiconductor layer over an oxide layer. An organic planarizing layer (OPL)-blocking structure is formed on one or more regions of the semiconductor layer which will block the one or more regions of the semiconductor layer from silicidation. At least one silicide metal is deposited on the wafer. The wafer is annealed to react the at least one silicide metal with one or more exposed regions of the semiconductor layer. Unreacted silicide metal is removed. Any remaining portions of the OPL-blocking structure are removed.

Abstract: A template material layer is deposited over a substrate, and is patterned with at least two trenches having different lengthwise directions. An array of polymer lines are formed by directed self-assembly of a copolymer material and a selective removal of one type of polymer material relative to another type within each trench such that the lengthwise direction of the polymer lines are parallel to the lengthwise sidewalls of the trench. The patterns in the arrays of polymer lines are transferred into an underlying material layer to form arrays of patterned material structures. The arrays of patterned material structures may be arrays of semiconductor material portion, or may be arrays of gate electrodes. An array of patterned material structures may be at a non-orthogonal angle with respect to an array of underlying material portions or with respect to an array of overlying material portions to be subsequently formed.

Abstract: A silicidation blocking process is provided. In one aspect, a silicidation method is provided. The method includes the following steps. A wafer is provided having a semiconductor layer over an oxide layer. An organic planarizing layer (OPL)-blocking structure is formed on one or more regions of the semiconductor layer which will block the one or more regions of the semiconductor layer from silicidation. At least one silicide metal is deposited on the wafer. The wafer is annealed to react the at least one silicide metal with one or more exposed regions of the semiconductor layer. Unreacted silicide metal is removed. Any remaining portions of the OPL-blocking structure are removed.

Abstract: A template material layer is deposited over a substrate, and is patterned with at least two trenches having different lengthwise directions. An array of polymer lines are formed by directed self-assembly of a copolymer material and a selective removal of one type of polymer material relative to another type within each trench such that the lengthwise direction of the polymer lines are parallel to the lengthwise sidewalls of the trench. The patterns in the arrays of polymer lines are transferred into an underlying material layer to form arrays of patterned material structures. The arrays of patterned material structures may be arrays of semiconductor material portion, or may be arrays of gate electrodes. An array of patterned material structures may be at a non-orthogonal angle with respect to an array of underlying material portions or with respect to an array of overlying material portions to be subsequently formed.

Abstract: A pair of electrode plates can be provided by directional deposition and patterning of a conductive material on sidewalls of a template structure on a first dielectric layer. An electrode line straddling the center portion is formed. A dielectric spacer and a conformal conductive layer are subsequently formed. Peripheral electrodes laterally spaced from the electrode line are formed by pattering the conformal conductive layer. After deposition of a second dielectric material layer that encapsulates the template structure, the template structure is removed to provide a cavity that passes through the pair of electrode plates, the electrode line, and the peripheral electrodes. A nanoscale sensor thus formed can electrically characterize a nanoscale string by passing the nanoscale string through the cavity while electrical measurements are performed employing the various electrodes.

Abstract: A post-planarization recess etch process is employed in combination with a replacement gate scheme to enable formation of multi-directional wiring in gate electrode lines. After formation of disposable gate structures and a planarized dielectric layer, a trench extending between two disposable gate structures are formed by a combination of lithographic methods and an anisotropic etch. End portions of the trench overlap with the two disposable gate structures. After removal of the disposable gate structures, replacement gate structures are formed in gate cavities and the trench simultaneously. A contiguous gate level structure can be formed which include portions that extend along different horizontal directions.

Abstract: Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a field effect transistor device is provided. The field effect transistor device includes a source region; a drain region; a plurality of fins connecting the source region and the drain region, the fins having a pitch of between about 40 nanometers and about 200 nanometers and each fin having a width of between about ten nanometers and about 40 nanometers; and a gate stack over at least a portion of the fins, wherein the source region and the drain region are self-aligned with the gate stack.

Abstract: Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.