Abstract: A method for programming a configuration bit including magnetic tunnel junctions (MTJs), including during a first phase: applying a first voltage to a first leg of MTJs and a third leg of MTJs to program or inhibit the MTJs of the first leg and the third leg, and applying a second voltage to a second leg of MTJs and a fourth leg of MTJs to program or inhibit the MTJs of the second leg and the fourth leg. During a second phase: applying the second voltage to the first leg of MTJs and the third leg of MTJs to program or inhibit the MTJs of the first leg and the third leg, and applying the first voltage to the second leg of MTJs and the fourth leg of MTJs to program or inhibit the MTJs of the second leg and the fourth leg.

Abstract: A memory device including an array circuit including a magnetic tunnel junction (MTJ) bit having a logical state and including a set of MTJs is provided. The memory device further includes a read device electrically connected to the MTJ bit and configured to read the logical state of the MTJ bit. The memory device includes a write circuit electrically connected to the MTJ bit and configured to write the logical state of the MTJ bit. The array circuit is powered off between operations on the MTJ bit by the read device and/or the write circuit.

Abstract: A memory device includes a magnetic tunnel junction (MTJ) array having a logical state and a capacitive net charged to a first voltage and electrically connected to the MTJ array. The memory device further includes a read device electrically connected to the MTJ array and configured to read the logical state of the MTJ array as the capacitive net discharges to a second voltage different than the first voltage.

Abstract: A magnetoresistive memory may include a plurality of magnetoresistive memory devices, wherein each magnetoresistive device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed between the fixed and free magnetic regions. The magnetoresistive memory may include a spin-orbit-torque (SOT) channel, wherein the SOT channel is in contact with the free magnetic regions of the plurality of magnetoresistive memory devices. The magnetoresistive memory may include a write circuit configured to apply a write current through at least one magnetoresistive memory device of the plurality of magnetoresistive memory devices and the SOT channel, wherein the write current is configured to generate a short in at least one magnetoresistive memory device as a one-time programmable read-only memory (ROM) function.

Abstract: An antifuse device may comprise an antifuse bit including: a first non-magnetic conductive layer, an insulator above the first non-magnetic conductive layer, and a second non-magnetic conductive layer above the insulator, wherein when the insulator is disrupted, the first non-magnetic conductive layer and the second non-magnetic conductive layer permanently conduct an electrical current from one to another.

Abstract: A device may include a set of antifuse magnetic tunnel junctions (MTJs). A device may include a trim-enable MTJ associated with the set of antifuse MTJs, wherein each of the set of antifuse MTJs and the trim-enable MTJ has a logical state, the logical state being a first logical state or a second logical state. A device may include a circuit configured to determine the logical state of each of the set of antifuse MTJs and the trim-enable MTJ, wherein the logical state of each antifuse MTJ in the set of antifuse MTJs is read when the trim-enable MTJ has the second logical state, and wherein the logical state of every antifuse MTJ in the set of antifuse MTJs is determined to be the first logical state when the trim-enable MTJ has the first logical state.

Abstract: A reference resistor in a magnetoresistive tunnel junction (MTJ) antifuse circuit is disclosed. The reference resistor has a variable resistance, and includes a first resistor having a first resistance, a set of second resistors each having a second resistance, and an electrical conductor layer configured to selectively electrically connect one or more second resistors in the set of second resistors to vary the variable resistance of the reference resistor.

Abstract: A memory device including a first configuration bit group including a plurality of bits, the plurality of bits including: a plurality of configuration bits; at least one redundant configuration bit; a plurality of configuration bit multiplexers each configured to receive (i) a first input from a first bit in the plurality of bits and/or a second input from a second bit in the plurality of bits and (ii) a third input from a decoder, each of the first, second, and third inputs indicating a respective logical state, wherein the logical state includes a first state or a second state; and wherein, based on the logical state of the third input received from the decoder, each configuration bit multiplexer is configured to output: the logical state of the first input from the first bit, or the logical state of the second input from the second bit.

Abstract: Memory built-in self-test (MBIST) circuitry for a disruptive memory includes an address sequencer configured to select an address with the disruptive memory as a test location, and control circuitry configured to direct a test sequence including a plurality of test operations on the test location. The control circuitry includes a first fault counter and a second fault counter, in which the control circuitry is configured to, after each test operation of the test sequence, determine whether to selectively update a first fault counter and whether to selectively update a second fault counter. The address sequencer, after completion of the test sequence, selects a next address within the disruptive memory as a next test location.

Abstract: Memory built-in self-test (MBIST) circuitry for a disruptive memory includes an address sequencer configured to select an address with the disruptive memory as a test location, and control circuitry configured to direct a test sequence including a plurality of test operations on the test location. The control circuitry includes a first fault counter and a second fault counter, in which the control circuitry is configured to, after each test operation of the test sequence, determine whether to selectively update a first fault counter and whether to selectively update a second fault counter. The address sequencer, after completion of the test sequence, selects a next address within the disruptive memory as a next test location.

Abstract: A memory includes a pair of sense amplifiers where the pair of sense amplifiers perform a multiphase memory operation to read data from two memory cells. Each sense amplifier includes two current paths. During a first phase of the memory read operation, one of the two sense amplifiers provides current through both a first memory cell and a first reference cell and the other sense amplifier of the two provides current through both a second memory cell and a second reference cell. The reference cells each have different resistance values. During a second phase of the memory read operation, one of the sense amplifiers provides current through both of the first memory cell and the second reference cell and the second sense amplifier provides current through the second memory cell and the first reference cell.

Abstract: A memory includes a pair of sense amplifiers where the pair of sense amplifiers perform a multiphase memory operation to read data from two memory cells. Each sense amplifier includes two current paths. During a first phase of the memory read operation, one of the two sense amplifiers provides current through both a first memory cell and a first reference cell and the other sense amplifier of the two provides current through both a second memory cell and a second reference cell. The reference cells each have different resistance values. During a second phase of the memory read operation, one of the sense amplifiers provides current through both of the first memory cell and the second reference cell and the second sense amplifier provides current through the second memory cell and the first reference cell.

Abstract: A memory includes a first memory cell; and a second memory cell. A selectable current path is coupled between the first memory cell and the second memory cell. The selectable current path includes a first transistor. A first amplifier is coupled in a first feedback arrangement between the first memory cell and the first transistor. During a read operation of the first memory cell, a current through the first memory cell is substantially equal to a current through the second memory cell. The memory cell may include a magnetic tunnel junction (MTJ).

Abstract: An integrated circuit includes a first plurality of flip flops; a first bank of resistive memory cells, wherein each flip flop of the first plurality of flip flops uniquely corresponds to a resistive memory cell of the first bank of resistive memory cells; write circuitry configured to store data from the first plurality of flip flops to the first bank of resistive memory cells; and read circuitry configured to read data from the first bank of resistive memory cells and provide the data from the first bank for storage into the first plurality of flip flops.

Abstract: A memory includes a global reference circuit for generating a signal that controls the resistance of a plurality of reference devices used to read data in memory cells by sense amplifiers of the memory. The signal is generated by an output of an operational amplifier of the global reference circuit. The operational amplifier includes a first input whose voltage is set by flowing current through a reference circuit and a second input whose voltage is set by flowing current through a master reference device. The signal controls the resistance of the master reference device such that the voltages of the inputs of the operational amplifier match.

Abstract: The present disclosure provides circuit and method embodiments for calibrating a signal of an integrated circuit. A programmable resistive element is coupled in series with a node of the integrated circuit, where at least part of the integrated circuit is formed in at least one front end of line (FEOL) device level. The programmable resistive element is formed in at least one back end of line (BEOL) wiring level, and the programmable resistive element is in a non-volatile resistive state that is variable across a plurality of non-volatile resistive states in response to a program signal applied to the programmable resistive element.

Abstract: A non-volatile flip flop integrated circuit includes a master latch circuit, a slave latch circuit coupled to the master latch circuit, and a non-volatile memory array coupled to the slave latch circuit. The non-volatile memory array includes a first pair of memory cells coupled to the slave latch circuit, and a second pair of memory cells coupled to the slave latch circuit in parallel with the first pair of memory cells. The first and second pair of memory cells are configured to store data from the slave latch circuit, and to restore data to the slave latch circuit.

Abstract: A non-volatile flip flop integrated circuit includes a master latch circuit, a slave latch circuit coupled to the master latch circuit, and a non-volatile memory array coupled to the slave latch circuit. The non-volatile memory array includes a first pair of memory cells coupled to the slave latch circuit, and a second pair of memory cells coupled to the slave latch circuit in parallel with the first pair of memory cells. The first and second pair of memory cells are configured to store data from the slave latch circuit, and to restore data to the slave latch circuit.

Abstract: A memory device includes a sense amplifier coupled to a first read voltage during a first phase of a read operation and a second read voltage during a second phase of the read operation. A first and second bias voltages are based on the first and second read voltages and corresponding current on a bit line. A first capacitor includes a terminal coupled to the first and second bias voltages. A first amplifier includes an input coupled to another terminal of the first capacitor and another input coupled to a common mode voltage during the first phase and to a reference voltage during the second phase. A second capacitor includes a terminal coupled to an output of the first amplifier. A second amplifier includes an inverting input coupled to another terminal of the second capacitor and another input coupled to a common mode voltage.

Abstract: An integrated circuit includes a first plurality of flip flops; a first bank of resistive memory cells, wherein each flip flop of the first plurality of flip flops uniquely corresponds to a resistive memory cell of the first bank of resistive memory cells; write circuitry configured to store data from the first plurality of flip flops to the first bank of resistive memory cells; and read circuitry configured to read data from the first bank of resistive memory cells and provide the data from the first bank for storage into the first plurality of flip flops.