Abstract: A method is provided for programming a multi-state flash memory having a plurality of memory cells. A first programming pulse is provided to the flash array; determining a threshold voltage distribution for the plurality of memory cells after providing the first programming pulse. The plurality of memory cells is categorized into at least two bins based on a threshold voltage of each memory cell of the plurality of memory cells. A first voltage is selected for a second programming pulse for programming a first bin of memory cells of the at least two bins, the first voltage based on both a threshold voltage of the first bin and a first target threshold voltage. A second voltage is selected for a third programming pulse for programming a second bin of memory cells of the at least two bins, the second voltage based on both the threshold voltage of the second bin and on a second target threshold voltage.

Abstract: A method includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage conditions based on the results from soft programming the first subset of bits is selected. A second subset of bits that have been over-erased are soft programmed. The soft programming applies the initial voltage condition to the bits in the second subset of bits. The second subset comprises bits that are still over-erased when the step of selecting occurs. The result is that the soft programming for the second subset may begin at a more optimum point for quickly achieving the needed soft programming to bring all of the bits within the desired erase condition.

Abstract: A process and device structure is provided for increasing capacitance density of a capacitor structure. A sandwich capacitor is provided in which a bottom silicon-containing conductor plate is formed with holes or cavities, upon which an oxide layer and a top silicon-containing layer conductor is formed. The holes or cavities provide additional capacitive area, thereby increasing capacitance per footprint area of the capacitor structure. The holes can form, for example, a line structure or a waffle-like structure in the bottom conductor plate. Etching techniques used to form the holes in the bottom conductor plate can also result in side wall tapering of the holes, thereby increasing the surface area of the silicon-containing layer defined by the holes. In addition, depth of holes can be adjusted through timed etching to further adjust capacitive area.

Abstract: A method is provided for programming a multi-state flash memory having a plurality of memory cells. A first programming pulse is provided to the flash array; determining a threshold voltage distribution for the plurality of memory cells after providing the first programming pulse. The plurality of memory cells is categorized into at least two bins based on a threshold voltage of each memory cell of the plurality of memory cells. A first voltage is selected for a second programming pulse for programming a first bin of memory cells of the at least two bins, the first voltage based on both a threshold voltage of the first bin and a first target threshold voltage. A second voltage is selected for a third programming pulse for programming a second bin of memory cells of the at least two bins, the second voltage based on both the threshold voltage of the second bin and on a second target threshold voltage.

Abstract: A method includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage conditions based on the results from soft programming the first subset of bits is selected. A second subset of bits that have been over-erased are soft programmed. The soft programming applies the initial voltage condition to the bits in the second subset of bits. The second subset comprises bits that are still over-erased when the step of selecting occurs. The result is that the soft programming for the second subset may begin at a more optimum point for quickly achieving the needed soft programming to bring all of the bits within the desired erase condition.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.

Abstract: A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.

Abstract: A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor structure and the layer of the gate material and the storage layer may be located closer to the first side of the second wafer than the semiconductor structure. The method further includes boding the first side of the second wafer to the first wafer. The method further includes removing a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a transistor having a channel region, wherein at least a portion of the channel region is formed from the layer of the semiconductor structure.

Abstract: A method is provided which includes forming a first gate overlying a major surface of an electronic device substrate and forming a second gate overlying and spaced apart from the first gate. The method further includes forming a charge storage structure horizontally adjacent to, and continuous along, the first gate and the second gate, wherein a major surface of the charge storage structure is substantially vertical to the major surface of the substrate.

Abstract: A process for forming an electronic device can include forming a trench within a substrate, wherein the trench includes a wall and a bottom. The process can also include including forming a portion of discontinuous storage elements that lie within the trench, and forming a first gate electrode within the trench after forming the discontinuous storage elements. At least one discontinuous storage element lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and a primary surface of the substrate. The process can also include forming a second gate electrode overlying the first gate electrode and the primary surface of the substrate.

Abstract: An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein at least one discontinuous storage element lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and a primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface of the substrate. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.

Abstract: A method for making a semiconductor device comprises providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor structure, a first storage layer, and a layer of gate material, wherein the first storage layer is located between the semiconductor structure and the layer of gate material and closer to the first side of the second wafer than the semiconductor structure. The method further includes bonding the first side of the second wafer to the first wafer and cleaving away a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a second storage layer over the layer of the semiconductor structure and forming a top gate over the second storage layer.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.

Abstract: A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.

Abstract: A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.

Abstract: A method of forming a semiconductor device, which is preferably a memory cell, includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, wherein each of the plurality of discrete storage elements has a diameter value that is approximately equal to each other, and forming a second dielectric layer over the plurality of discrete storage elements, wherein the second dielectric layer has a thickness, wherein the ratio of the thickness of the second dielectric to the diameter value is less than approximately 0.8. The spacing between the plurality of discrete storage elements may be greater than or equal to approximately the thickness of the second dielectric layer.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.

Abstract: A voltage controlled oscillator (VCO) has a plurality of series-connected inverters. Within each inverter a first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series-connected inverters, and a second control electrode for receiving a first bias signal. A second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

Abstract: In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.