Patents by Inventor Michael A. VanBuskirk
Michael A. VanBuskirk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070064464Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.Type: ApplicationFiled: September 20, 2005Publication date: March 22, 2007Inventors: Tiao-Hua Kuo, Nancy Leong, Nian Yang, Guowei Wang, Aaron Lee, Sachit Chandra, Michael VanBuskirk, Johnny Chen, Darlene Hamilton, Binh Le
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Publication number: 20060221713Abstract: A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy.Type: ApplicationFiled: March 31, 2005Publication date: October 5, 2006Inventors: Michael VanBuskirk, Colin Bill, Zhida Lan, Tzu-Ning Fang
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Publication number: 20060104111Abstract: The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor.Type: ApplicationFiled: November 17, 2004Publication date: May 18, 2006Inventors: Nicholas Tripsas, Colin Bill, Michael VanBuskirk, Matthew Buynoski, Tzu-Ning Fang, Wei Cai, Suzette Pangrle, Steven Avanzino
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Patent number: 7035141Abstract: The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages.Type: GrantFiled: November 17, 2004Date of Patent: April 25, 2006Inventors: Nicholas H. Tripsas, Colin S. Bill, Michael A. VanBuskirk, Matthew Buynoski, Tzu-Ning Fang, Wei Daisy Cai, Suzette Pangrle, Steven Avanzino
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Publication number: 20060038169Abstract: Systems and methodologies are provided for of enabling a polymer memory cell to exhibit variable retention times for stored data therein. Such setting of retention time can depend upon a programming mode and/or type of material employed in the polymer memory cell. Short retention times can be obtained by programming the polymer memory cell via a low current or a low electrical field. Similarly, long retention times can be obtained by employing a high current or electrical field to program the polymer memory cell.Type: ApplicationFiled: August 17, 2004Publication date: February 23, 2006Applicant: SPANSION, LLCInventors: Aaron Mandell, Michael VanBuskirk, Stuart Spitzer, Juri Krieger
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Patent number: 6979837Abstract: The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers—respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device.Type: GrantFiled: May 19, 2004Date of Patent: December 27, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Nicholas H. Tripsas, Uzodinma Okoroanyanwu, Suzette K. Pangrle, Michael A. VanBuskirk
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Patent number: 6960783Abstract: An organic memory cell made of two electrodes with a selectively conductive media between the two electrodes is disclosed. The selectively conductive media contains an organic layer and passive layer. The selectively conductive media is programmed by applying bias voltages that program a desired impedance state for a memory cell. The desired impedance state represents one or more bits of information and the memory cell does not require constant power or refresh cycles to maintain the desired impedance state. Furthermore, the selectively conductive media is read by applying a current and reading the impedance of the media in order to determine the impedance state of the memory cell. Methods of making the organic memory devices/cells, methods of using the organic memory devices/cells, and devices such as computers containing the organic memory devices/cells are also disclosed.Type: GrantFiled: May 13, 2003Date of Patent: November 1, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Zhida Lan, Colin Bill, Michael A. VanBuskirk
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Patent number: 6943370Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.Type: GrantFiled: June 30, 2004Date of Patent: September 13, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Michael A. VanBuskirk, Colin Bill, Tzu-Ning Fang, Zhida Lan
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Patent number: 6870183Abstract: The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers—respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device.Type: GrantFiled: November 4, 2002Date of Patent: March 22, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Nicholas H. Tripsas, Uzodinma Okoroanyanwu, Suzette K. Pangrle, Michael A. VanBuskirk
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Patent number: 6847047Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.Type: GrantFiled: November 4, 2002Date of Patent: January 25, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Michael A. VanBuskirk, Colin Bill, Tzu-Ning Fang, Zhida Lan
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Publication number: 20040245522Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.Type: ApplicationFiled: June 30, 2004Publication date: December 9, 2004Inventors: Michael A. VanBuskirk, Colin Bill, Tzu-Ning Fang, Zhida Lan
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Publication number: 20040227136Abstract: An organic memory cell made of two electrodes with a selectively conductive media between the two electrodes is disclosed. The selectively conductive media contains an organic layer and passive layer. The selectively conductive media is programmed by applying bias voltages that program a desired impedance state for a memory cell. The desired impedance state represents one or more bits of information and the memory cell does not require constant power or refresh cycles to maintain the desired impedance state. Furthermore, the selectively conductive media is read by applying a current and reading the impedance of the media in order to determine the impedance state of the memory cell. Methods of making the organic memory devices/cells, methods of using the organic memory devices/cells, and devices such as computers containing the organic memory devices/cells are also disclosed.Type: ApplicationFiled: May 13, 2003Publication date: November 18, 2004Inventors: Zhida Lan, Colin Bill, Michael A. VanBuskirk
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Publication number: 20040217347Abstract: The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers—respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device.Type: ApplicationFiled: May 19, 2004Publication date: November 4, 2004Inventors: Nicholas H. Tripsas, Uzodinma Okoroanyanwu, Suzette K. Pangrle, Michael A. VanBuskirk
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Publication number: 20040084743Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.Type: ApplicationFiled: November 4, 2002Publication date: May 6, 2004Inventors: Michael A. VanBuskirk, Colin Bill, Tzu-Ning Fang, Zhida Lan
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Publication number: 20040084670Abstract: The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers—respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device.Type: ApplicationFiled: November 4, 2002Publication date: May 6, 2004Inventors: Nicholas H. Tripsas, Uzodinma Okoroanyanwu, Suzette K. Pangrle, Michael A. VanBuskirk
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Publication number: 20030218913Abstract: A method of erasing a sector of flash memory cells wherein a first set of preset pre-erase voltages is applied to the sector of flash memory cells. After the first set of preset pre-erase voltages is applied it is determined if another set of preset pre-erase voltages is to be applied to the sector of flash memory cells. If another set of preset pre-erase voltages is applied and if another set of preset pre-erase set of pre-erase voltages is not to be applied, a standard erase routine is applied to the sector.Type: ApplicationFiled: May 24, 2002Publication date: November 27, 2003Inventors: Binh Quang Le, Darlene Hamilton, Kulachet Tanpairoj, Zhizheng Liu, Yi He, Wei Zheng, Pau-Ling Chen, Michael Vanbuskirk
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Patent number: 6622201Abstract: A sequential access memory structure includes an output bus and a plurality of sequential access memories, each of which is connected to the output bus. Each memory includes a memory array having a plurality of sequentially readable memory elements, a carry output for producing a carry signal when reading of the array has been substantially completed, and a carry input for causing reading of the array in response to a carry signal. The carry output of each memory is connected to a carry input of one other downstream memory respectively in a chain arrangement, and the carry signals cause the arrays to be read sequentially onto the output bus. Each memory further comprises a read-write storage connected between the array and the output bus, the storage including a plurality of sections. Data from the array is loaded into one section of the storage while data is being read from another section of the storage onto the output bus. The sections of memory elements in the array comprise half-pages.Type: GrantFiled: March 14, 2000Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Michael VanBuskirk, Pau-Ling Chen
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Patent number: 6163481Abstract: A wordline tracking structure for use in an array of Flash EEPROM memory cells is provided. The tracking structure serves to match reference and sector core wordline voltages across the entire chip regardless of sector location. The tracking structure includes a second VPXG conductor line operatively connected between sector wordlines of a "far" sector and a reference cell mini-array. The second VPXG conductor line has a substantially smaller time constant than in a first VPXG conductor line operatively connected between an output of a boosting circuit and the sector wordlines of the "far" sector. As a consequence, the reference wordline voltage associated with the reference cell mini-array will track closely the sector wordline voltage during the read operation regardless of the location of the selected sector.Type: GrantFiled: October 29, 1999Date of Patent: December 19, 2000Assignees: Advanced Micro Devices, Inc., Fujitsu LimitedInventors: Shigekasu Yamada, Colin S. Bill, Michael A. VanBuskirk