Patents by Inventor Michael A. Zampaglione
Michael A. Zampaglione has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9722605Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: April 25, 2016Date of Patent: August 1, 2017Assignee: Conversant Intellectual Property Management Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20160315615Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: April 25, 2016Publication date: October 27, 2016Applicant: Conversant Intellectual Property Management Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 9350349Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: September 8, 2014Date of Patent: May 24, 2016Assignee: Conversant Intellectual Property Management Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20140375354Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: September 8, 2014Publication date: December 25, 2014Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 8854077Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: August 8, 2012Date of Patent: October 7, 2014Assignee: Conversant Intellectual Property Management Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20130027125Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: August 8, 2012Publication date: January 31, 2013Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 8253438Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: March 29, 2011Date of Patent: August 28, 2012Assignee: Mosaid Technologies IncorporatedInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20110260785Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: March 29, 2011Publication date: October 27, 2011Applicant: MOSAID Technologies IncorporatedInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 7940081Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: August 17, 2009Date of Patent: May 10, 2011Assignee: MOSAID Technologies IncorporatedInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20100060319Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: August 17, 2009Publication date: March 11, 2010Applicant: MOSAID Technologies CorporationInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 7592837Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: September 19, 2008Date of Patent: September 22, 2009Assignee: MOSAID Technologies CorporationInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20090027080Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: September 19, 2008Publication date: January 29, 2009Applicant: Mosaid Technologies, Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 7443197Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: November 30, 2007Date of Patent: October 28, 2008Assignee: Mosaid Technologies, Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20080084775Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: November 30, 2007Publication date: April 10, 2008Inventors: Barry Hoberman, Daniel Hillman, William Walker, John Callahan, Michael Zampaglione, Andrew Cole
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Patent number: 7348804Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: April 2, 2007Date of Patent: March 25, 2008Assignee: MOSAID Delaware, Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20070252623Abstract: A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of Vdd?(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.Type: ApplicationFiled: April 27, 2007Publication date: November 1, 2007Applicant: MOSAID TECHNOLOGIES CORPORATIONInventors: Michael Zampaglione, Michael Tooher
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Publication number: 20070176639Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: April 3, 2007Publication date: August 2, 2007Inventors: Barry Hoberman, Daniel Hillman, William Walker, John Callahan, Michael Zampaglione, Andrew Cole
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Patent number: 7227383Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: January 20, 2005Date of Patent: June 5, 2007Assignee: Mosaid Delaware, Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 7051308Abstract: Methods are apparatuses are disclosed for library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.Type: GrantFiled: June 3, 2002Date of Patent: May 23, 2006Assignee: Virtual Silicon Technology, Inc.Inventors: Michael J. McManus, Billie J. Rivera, Richard Talburt, William G. Walker, Michael A. Zampaglione
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Publication number: 20050184758Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: January 20, 2005Publication date: August 25, 2005Inventors: Barry Hoberman, Daniel Hillman, William Walker, John Callahan, Michael Zampaglione, Andrew Cole