Abstract: Methods are apparatuses are disclosed for an electrical apparatus. The electrical apparatus includes one or more integrated circuits designed at least partly with library cells. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

Abstract: Methods are apparatuses are disclosed for a software tool adapted to function with at least library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

Abstract: Methods are apparatuses are disclosed for library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

Abstract: Methods are apparatuses are disclosed for an electrical apparatus. The electrical apparatus includes one or more integrated circuits designed at least partly with library cells. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

Abstract: Methods are apparatuses are disclosed for a software tool adapted to function with at least library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

Abstract: A block compiler system that allows a user to specify the total number of words and bits per word in a memory structure and to choose among alternative memory structures according to a user-selected criterion. In operation, the system varies the partitioning of memory address lines among column address lines and row address lines. Further, the system varies the internal memory structure according to a selected partitioning of memory address lines among column address lines and row address lines, and optimizes the memory structure based upon higher-level user-selected criteria.

Abstract: A method for producing an electrical circuit by determining the input-to-output timing of compiled circuit blocks includes steps of determining a signal delay of a component due to physical characteristics of the component. The physical characteristics include at least a capacitance based upon relative placement of the component during compilation of a circuit block. The method further includes steps of determining an input-to-output speed for a circuit block by combining delays due to physical characteristics through alternate paths of the circuit block, and producing a compiled circuit block having a plurality of components by placing the components in the circuit block based on the steps of determining.

Abstract: Methods and devices for efficiently using substrate space to form memory devices on integrated circuits, and in particular, in application specific integrated circuits. More particularly, a shared decoder and control logic are used for selectively accessing and addressing plural types of memory (e.g., RAM and ROM cells). Further, each memory cell of a memory array is programmed as a particular type of memory cell during circuit layout design. Therefore, specific rows, columns, or single bits of the memory cell array can be designated as specific types of memory.

Abstract: A method for compensating for bit line delays in semiconductor memories including the steps of developing a dummy word line signal representative of the delay of a word line of a semiconductor memory and controlling the sense amplifier of the semiconductor memory with a control signal derived, at least in part, from the dummy word line signal. Preferably, the dummy word line signal is delayed by a fixed delay or by delay produced by a proportionally loaded dummy bit line. A circuit embodying the method of the present invention includes a dummy word which produces a dummy word signal upon the activation of any word of the semiconductor memory and a delay coupling the dummy word signal to the clock input of the sense amplifier. The delay may be a fixed delay including a number of logic elements, or it may be developed by a proportionally loaded bit line which has a fraction of the load of an actual bit line of the semiconductor memory.

Abstract: A buffer characterized by a pull-up network and a pull-down network which are both coupled between an input and an output of the buffer. Each of the networks include a number of switch elements which can be sequentially turned on or off by means of an RC network to provide slew-rate control for the buffer. Preferably, each of the networks are associated with diode bypass networks to reduce crowbar current. In operation, both the pull-up network and the pull-down network turn on slowly but turn off very quickly due to the diode bypass networks.

Abstract: A buffer characterized by a pull-up network and a pull-down network which are both coupled between an input and an output of the buffer. Each of the networks include a number of switch elements which can be sequentially turned on or off by means of an RC network to provide slew-rate control for the buffer. Preferably, each of the networks are associated with diode bypass networks to reduce crowbar current. In operation, both the pull-up network and the pull-down network turn on slowly but turn off very quickly due to the diode bypass networks.