Abstract: Techniques for fast ramp, low supply charge-pump circuits are described herein. In an example embodiment, a non-volatile memory device comprises a flash memory array coupled to a fast charge-pump circuit. The charge-pump circuit comprises a first charge pump, an active charge pump coupled as input to the first charge pump, and a power supply coupled as input to the active charge pump. The active charge pump is configured to initialize the first charge pump to a greater absolute voltage than the power supply and to provide power to the first charge pump during an active mode of the flash memory array.

Abstract: Techniques for fast ramp, low supply charge-pump circuits are described herein. In an example embodiment, a non-volatile memory device comprises a flash memory array coupled to a fast charge-pump circuit. The charge-pump circuit comprises a first charge pump, an active charge pump coupled as input to the first charge pump, and a power supply coupled as input to the active charge pump. The active charge pump is configured to initialize the first charge pump to a greater absolute voltage than the power supply and to provide power to the first charge pump during an active mode of the flash memory array.

Abstract: A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.

Abstract: An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.

Abstract: A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.

Abstract: Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.

Abstract: A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage.

Abstract: Providing systems and methods that reduce memory device read errors and improve memory device reliability by intelligently disturbing the memory cells during storage of their characteristic states. A specification component can determine a desired characteristic state for each cell of a plurality of multi-cell memory devices. A storage component can, alternatively, successively store an equivalent characteristic state in each cell of the plurality of multi-cell memory devices in stages, based on a cell's current characteristic state, or directly store the desired characteristic state of each cell of the plurality of multi-cell memory devices, based on an ordering of desired characteristic states of cells of the multi-cell memory devices. Further, a step component can gradate the equivalent characteristic state between successive storage stages. In this way, the overlap of distributions of electrical characteristics associated with different bits of one or more memory cells can be reduced.

Abstract: A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells.

Abstract: Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one or more values of the one or more characteristics of the memory cell, the computation component computes one or more programming pulses as a function of the one or more measured values of the one or more characteristics of the memory cell, and the pulse component applies the one or more programming pulses to the memory cell.

Abstract: Systems, methods, and devices that employ deterministic programming techniques to facilitate efficient programming of memory elements in a memory are presented. A memory component comprises an optimized program component that can divide a group of memory elements selected for programming into a desired number of subgroups based in part on respective current threshold voltage levels (Vt) of the memory elements; apply respective program pulses to each memory element in respective subgroups; measure respective Vt levels of memory elements after the pulse; and verify as passed memory elements that meet a target Vt. The optimized program component can divide a subset of memory elements that do not meet the target Vt into a desired number of subgroups based in part on respective current Vt levels of the memory elements and can continue to perform this deterministic programming process until all memory elements are verified as passing for the target Vt.

Abstract: Providing distinction between overlapping threshold levels of one or more multi-cell memory devices is described herein. By way of example, a system can include a sensing component that can measure a level associated with a first memory cell. The system can also include a comparison component that can compare the measured level associated with the first memory cell level to non-overlapping threshold levels, wherein such measurement can be used to determine a unique bit level associated with a second memory cell. By way of further example, methodologies are described for accurately measuring a bit level of a first cell of a dual-cell memory device, by comparing a second cell value to non-overlapping threshold values, as measured with respect to the second reference point.

Abstract: Flash memory devices have a plurality of memory cells that can be erased and programmed. Performing a voltage verification check allows a for an appropriate state-change voltage to be applied to the flash memory device. The appropriate state-change voltage is determined though accessing a look-up table. Using an appropriate state-change voltage allows a cell to operate with more overall programming cycles.

Abstract: A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage.

Abstract: Application of too much voltage to a memory cell will cause damage to the cell or even destroy the cell. Tracking current that arises from an application of voltage upon a memory cell allows for minimization of damage upon the memory cell. If there is a change in current, then the voltage application can be accordingly changed.

Abstract: A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage.

Abstract: Systems, methods, and devices that employ deterministic programming techniques to facilitate efficient programming of memory elements in a memory are presented. A memory component comprises an optimized program component that can divide a group of memory elements selected for programming into a desired number of subgroups based in part on respective current threshold voltage levels (Vt) of the memory elements; apply respective program pulses to each memory element in respective subgroups; measure respective Vt levels of memory elements after the pulse; and verify as passed memory elements that meet a target Vt. The optimized program component can divide a subset of memory elements that do not meet the target Vt into a desired number of subgroups based in part on respective current Vt levels of the memory elements and can continue to perform this deterministic programming process until all memory elements are verified as passing for the target Vt.

Abstract: Providing systems and methods that reduce memory device read errors and improve memory device reliability by intelligently disturbing the memory cells during storage of their characteristic states. A specification component can determine a desired characteristic state for each cell of a plurality of multi-cell memory devices. A storage component can, alternatively, successively store an equivalent characteristic state in each cell of the plurality of multi-cell memory devices in stages, based on a cell's current characteristic state, or directly store the desired characteristic state of each cell of the plurality of multi-cell memory devices, based on an ordering of desired characteristic states of cells of the multi-cell memory devices. Further, a step component can gradate the equivalent characteristic state between successive storage stages. In this way, the overlap of distributions of electrical characteristics associated with different bits of one or more memory cells can be reduced.

Abstract: A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage.

Abstract: An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines.