Patents by Inventor Michael Apodaca

Michael Apodaca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180293703
    Abstract: An embodiment of a graphics apparatus may include an embedded local memory, and a memory extender communicatively coupled to the embedded local memory to extend the embedded local memory. The memory extender may be configured to compress information and store the compressed information in the embedded local memory. Additionally, or alternatively, the memory extender may be configured to expose the embedded local memory for non-local access. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Karthik Vaidyanathan, Prasoonkumar Surti, Michael Apodaca, Murali Ramadoss, Abhishek Venkatesh, Joydeep Ray, Abhishek R. Appu
  • Publication number: 20180293760
    Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Karthik Vaidyanathan, Prasoonkumar Surti, Hugues Labbe, Atsuo Kuwahara, Sameer Kp, Jonathan Kennedy, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh
  • Publication number: 20180293106
    Abstract: Various embodiments are presented herein that may allow an application direct access to graphical processing unit memory. An apparatus and a computer-implemented method may include accessing allocated graphical processing unit memory of a second resource via a link from a first resource. The allocated graphical processing unit memory may be mapped into one or more page tables of a central processing unit. A virtual address of the graphical processing unit memory from the one or more page tables of the central processing unit may be sent to the application.
    Type: Application
    Filed: January 8, 2018
    Publication date: October 11, 2018
    Applicant: INTEL CORPORATION
    Inventor: Michael Apodaca
  • Publication number: 20180293699
    Abstract: An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Abhishek Venkatesh, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Prasoonkumar Surti
  • Publication number: 20180286115
    Abstract: An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh, Devan Burke, Philip R. Laws, Subramaniam Maiyuran, Abhishek R. Appu, ElMoustapha Ould-Ahmed-Vall, Peter L. Doyle
  • Publication number: 20180286112
    Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Andrew T. Lauritzen, Altug Koker, Louis Feng, Tomasz Janczak, David M. Cimini, Karthik Vaidyanathan, Abhishek Venkatesh, Murali Ramadoss, Michael Apodaca, Prasoonkumar Surti
  • Publication number: 20180285109
    Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Altug Koker, Michael Apodaca, Kai Xiao, Chandrasekaran Sakthivel, Jeffery S. Boles, Adam T. Lake, Abhishek R. Appu
  • Publication number: 20180286009
    Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.
    Type: Application
    Filed: May 30, 2018
    Publication date: October 4, 2018
    Inventors: JEFFERY S. BOLES, HEMA C. NALLURI, BALAJI VEMBU, MICHAEL APODACA, ALTUG KOKER, LALIT K. SAPTARSHI
  • Publication number: 20180286106
    Abstract: A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Michael Apodaca, Prasoonkumar Surti, Karthik Vaidyanathan, Murali Ramadoss, Abhishek Venkatesh, Jonathan Kennedy, Slawomir Grajewski
  • Patent number: 10068307
    Abstract: The same set of render commands can be re-executed for each of a plurality of tiles making up a graphic scene to be rendered. Each time the list of commands is executed, the way the commands are executed may be modified based on information received from tile pre-processing. Specifically, a jump if command may be inserted into the command list. When this command is encountered, a determination is made, based on information received from tile pre-processing pipeline, whether to execute the command for the next primitive or not. If the next primitive is to be culled then the command for the next primitive is not executed and the flow moves past that command. If the next primitive is to be executed then the jump is not implemented. This enables avoiding reloading the same list of commands over and over for every tile.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Balaji Vembu, Peter L. Doyle, Michael Apodaca, Hema C. Nalluri, Jeffery S. Boles
  • Patent number: 10013734
    Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Jeffery S. Boles, Hema C. Nalluri, Balaji Vembu, Michael Apodaca, Altug Koker, Lalit K. Saptarshi
  • Publication number: 20180144436
    Abstract: Various embodiments are presented herein that may reduce the workload of a system tasked with delivering frames of video data to a display generated by applications executing within the system. Applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). The CPU and/or GPU may be responsible for actually generating the frames at the specified FPS. These frames are then delivered to a display communicatively coupled with the system for rendering. Reducing the frame rate (FPS) may reduce the work being performed by the system because fewer frames may be generated within a given time period. This may be especially advantageous when the system is operating on battery power because it can extend the life of the battery.
    Type: Application
    Filed: August 28, 2017
    Publication date: May 24, 2018
    Applicant: INTEL CORPORATION
    Inventor: Michael APODACA
  • Publication number: 20180121368
    Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to build a command buffer without knowledge whether the contents of a cache will be discarded, and a memory to store the command buffer. The processor is to determine a discard state of the cache prior to executing the command buffer, execute the command buffer, and discard or keep the contents of the cache according to the discard state.
    Type: Application
    Filed: October 28, 2016
    Publication date: May 3, 2018
    Inventor: Michael Apodaca
  • Publication number: 20180081429
    Abstract: A virtual reality apparatus and method are described.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Inventors: TOMAS G. AKENINE-MOLLER, ROBERT M. TOTH, INGO WALD, ADITYA S. YANAMANDRA, BRENT E. INSKO, MICHAEL APODACA, PRASOONKUMAR SURTI
  • Patent number: 9916634
    Abstract: A mechanism is described for facilitating efficient graphics command generation and execution for improved graphics performance at computing devices. A method of embodiments, as described herein, includes detecting an application programming interface (API) call to perform a plurality of transactions, where the API call is issued by an application at a first command buffer, where the plurality of transactions include a first set of transactions and a second set of transactions. The method may further include creating a second command buffer and appending the second command buffer to the first command buffer, where creating further includes separating the first set transactions from the second set of transactions. The method may further include executing, via the second command buffer, the first set of transactions, prior to executing the first set of transactions.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: March 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Michael Apodaca, David M. Cimini
  • Patent number: 9881352
    Abstract: A mechanism is described for facilitating efficient processing of graphics commands at computing devices. A method of embodiments, as described herein, includes detecting a current object representing a bundled state of graphics commands in a command list to be processed at a graphics processor of a computing device, and evaluating the current object to determine a previous object bound to a first set of the graphics commands, where the first set of the graphics commands is associated with a first command state corresponding to the previous object. The method may further include copying a second set of the graphics commands to a command buffer associated with the command list, where the second set of the graphics commands represents a remainder of the graphics commands in the command list upon excluding the first set of the graphics commands. The method may further include facilitating the graphics processor to execute the second set of the graphics commands from the command buffer.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: January 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Michael Apodaca, Siddharth Y. Dharmadhikari
  • Publication number: 20180012328
    Abstract: A mechanism for command stream processing is described. A method of embodiments, as described herein, includes fetching cache lines from a memory to fill command first in first out buffer (FIFO), wherein the fetched cachelines an overfetching of data necessary to process a command, a first parser to fetch and execute batch commands stored in the command FIFO and a second parser to fetch commands and execute the batch commands and non-batch commands stored in the command FIFO.
    Type: Application
    Filed: July 7, 2016
    Publication date: January 11, 2018
    Inventors: Jeffery S. Boles, HEMA C. NALLURI, BALAJI VEMBU, PRITAV H. SHAH, MICHAEL APODACA, MURALI RAMADOSS, LALIT K. SAPTARSHI
  • Patent number: 9864638
    Abstract: Various embodiments are presented herein that may allow an application direct access to graphical processing unit memory. An apparatus and a computer-implemented method may include accessing allocated graphical processing unit memory of a second resource via a link from a first resource. The allocated graphical processing unit memory may be mapped into one or more page tables of a central processing unit. A virtual address of the graphical processing unit memory from the one or more page tables of the central processing unit may be sent to the application.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: January 9, 2018
    Assignee: INTEL CORPORATION
    Inventor: Michael Apodaca
  • Publication number: 20180005345
    Abstract: Methods and apparatus relating to reducing memory latency in graphics operations are described. In an embodiment, uniform data is transferred from a buffer to a General Register File (GRF) of a processor based at least in part on information stored in a gather table. The uniform data comprises data that is uniform across a plurality of primitives in a graphics operation. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Applicant: Intel Corporation
    Inventors: Michael Apodaca, David M. Cimini, Thomas F. Raoux, Somnath Ghosh, Uddipan Mukherjee, Debraj Bose, Sthiti Deka, Yohai Gevim
  • Publication number: 20170337656
    Abstract: The same set of render commands can be re-executed for each of a plurality of tiles making up a graphic scene to be rendered. Each time the list of commands is executed, the way the commands are executed may be modified based on information received from tile pre-processing. Specifically, a jump if command may be inserted into the command list. When this command is encountered, a determination is made, based on information received from tile pre-processing pipeline, whether to execute the command for the next primitive or not. If the next primitive is to be culled then the command for the next primitive is not executed and the flow moves past that command. If the next primitive is to be executed then the jump is not implemented. This enables avoiding reloading the same list of commands over and over for every tile.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 23, 2017
    Inventors: Balaji Vembu, Peter L. Doyle, Michael Apodaca, Hema C. Nalluri, Jeffery S. Boles