Abstract: An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.

Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Abstract: Various embodiments enable loop processing in a command processing block of the graphics hardware. Such hardware may include a processor including a command buffer, and a graphics command parser. The graphics command parser to load graphics commands from the command buffer, parse a first graphics command, store a loop count value associated with the first graphics command, parse a second graphics command and store a loop wrap address based on the second graphics command. The graphics command parser may execute a command sequence identified by the second graphics command, parse a third graphics command, the third graphics command identifying an end of the command sequence, set a new loop count value, and iteratively execute the command sequence using the loop wrap address based on the new loop count value.

Abstract: An apparatus and method for collecting and using profile data during graphics processing. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics commands responsive to execution of an application; and profile storage to store graphics execution profile data associated with one or more graphics workloads; and a profile manager to read the profile data upon detecting one of the graphics workloads during execution of the application and to configure the graphics processor in accordance with the profile data.

Abstract: An apparatus and method are described for culling commands in a tile-based renderer. For example, one embodiment of an apparatus comprises: a command buffer to store a plurality of commands to be executed by a render pipeline to render a plurality of tiles; visibility analysis circuitry to determine per-tile visibility information for each of the plurality of tiles and to store the visibility information for a first tile in a first storage, the visibility information specifying either that all of the commands associated with rendering the first tile can be skipped or identifying individual commands associated with rendering the first tile that can be skipped; and a render pipeline to read the visibility information from the first storage to determine whether to execute or skip one or more of the commands from the command buffer to render the first tile.

Abstract: By scheduling/managing workload submission to a position only shading pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments. An interface submits workloads to a slave engine running in one parallel pipe to assist a main engine running in another parallel pipe. Command sequences for each parallel pipe are separated to enable the slave engine to run ahead of the main engine. The slave engine is a position only shader and the main engine is a render engine.

Abstract: An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.

Abstract: A mechanism for command stream processing is described. A method of embodiments, as described herein, includes fetching cache lines from a memory to fill command first in first out buffer (FIFO), wherein the fetched cachelines an overfetching of data necessary to process a command, a first parser to fetch and execute batch commands stored in the command FIFO and a second parser to fetch commands and execute the batch commands and non-batch commands stored in the command FIFO.

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

Abstract: Various embodiments are presented herein that may reduce the workload of a GPU tasked with delivering frames of video data to a display generated by a 3D application executing within a system or computing platform. 3D applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). These frames are then delivered to a display communicatively coupled with the system for rendering. Every display has a refresh rate specified in cycles per second or Hertz (Hz). Vertical Synchronization (VSYNC) is a setting that synchronizes the frames per second (FPS) of a given application with the display's refresh rate. Forcing VSYNC on the application while the system is operating on battery power may reduce the workload on the GPU when the FPS is greater than the refresh rate resulting in greater battery life.

Abstract: Various embodiments are presented herein that may reduce the workload of a system tasked with delivering frames of video data to a display generated by applications executing within the system. Applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). The CPU and/or GPU may be responsible for actually generating the frames at the specified FPS. These frames are then delivered to a display communicatively coupled with the system for rendering. Reducing the frame rate (FPS) may reduce the work being performed by the system because fewer frames may be generated within a given time period. This may be especially advantageous when the system is operating on battery power because it can extend the life of the battery.

Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.

Abstract: Systems, apparatuses and methods may provide for technology that determines a frame rate of video content, sets a blend amount parameter based on the frame rate, and temporally anti-aliases the video content based on the blend amount parameter. Additionally, the technology may detect a coarse pixel (CP) shading condition with respect to one or more frames in the video content and select, in response to the CP shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is temporally anti-aliased based on the per frame jitter pattern. The CP shading condition may also cause the technology to apply a gradient to a plurality of color planes on a per color plane basis and discard pixel level samples associated with a CP if all mip data corresponding to the CP is transparent or shadowed out.

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

Abstract: Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.

Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

Abstract: An embodiment of a graphics apparatus may include an embedded local memory, and a memory extender communicatively coupled to the embedded local memory to extend the embedded local memory. The memory extender may be configured to compress information and store the compressed information in the embedded local memory. Additionally, or alternatively, the memory extender may be configured to expose the embedded local memory for non-local access. Other embodiments are disclosed and claimed.