Abstract: An integrated circuit optical die test interface and associated testing method are described for using scribe area optical mirror structures (106) to perform wafer die tests on MEMS optical beam waveguide (112) and optical circuit elements (113) by perpendicularly deflecting optical test signals (122) from the scribe area optical mirror structures (106) into and out of the plane of the integrated circuit die under test (104) and/or production test die (157).

Abstract: The dies of a stacked die IC are tested and, in response to detection of a defect at one of the dies, the type of defect is identified. If the defect is identified as a defective module repairable at the die itself, a redundant module of the die is used to replace the functionality of the defective module. If the defect is identified as one that is not repairable, a replacement die in the die stack is used to replace the functionality of the defective die.

Abstract: The dies of a stacked die integrated circuit (IC) employ the address bus to indicate the particular die, or set of dies, targeted by data on a data bus. During manufacture of the stacked die IC, the IC is programmed with information indicating a width of the address bus. During operation, each die addresses the other dies with addresses having the corresponding width based on this programmed information.

Abstract: An integrated circuit optical backplane die and associated semiconductor fabrication process are described for forming optical backplane mirror structures for perpendicularly deflecting optical signals out of the plane of the optical backplane die by selectively etching an optical waveguide semiconductor layer (103) on an optical backplane die wafer using an orientation-dependent anisotropic wet etch process to form a first recess opening (107) with angled semiconductor sidewall surfaces (106) on the optical waveguide semiconductor layer, where the angled semiconductor sidewall surfaces (106) are processed to form an optical backplane mirror (116) for perpendicularly deflecting optical signals to and from a lateral plane of the optical waveguide semiconductor layer.

Abstract: A high density, low power, high performance information system, method and apparatus are described in which an integrated circuit apparatus includes a first integrated circuit link element (657) and a redundant integrated circuit link element (660) connected in parallel between first and second deflectable MEMS switches (652-655, 662-665) which are connected in a signal path and controlled to deselect the first integrated circuit link element (657) and connect the redundant integrated circuit link element (660) in the signal path in response to a two-state control signal provided to the first and second deflectable MEMs switches which identifies the first integrated circuit link element as being defective.

Abstract: A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (D1-D8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.

Abstract: A high density, low power, high performance information system, method and apparatus are described in which an integrated circuit apparatus includes a plurality of deflectable MEMS optical beam waveguides (e.g., 190) at each die edge which are each formed with an optical beam structure (193) which is encapsulated by a waveguide beam structure (194) to extend into a deflection cavity (198) and which is surrounded by a plurality of deflection electrodes (195-197) that are positioned on walls of the deflection cavity (198) to provide two-dimensional deflection control of each deflectable MEMS optical beam waveguide in response to application of one or more deflection voltages to provide optical communications (e.g., 184) between different die.

Abstract: A method of manufacturing a microelectronic assembly (100) and a microelectronic device (4100) that include a stacked structure (101). The stacked structure includes a heat spreader (104), at least one die (106) thermally coupled to at least a portion of one side of the heat spreader, at least one other die (108) thermal coupled to at least a portion of an opposite side of the heat spreader, at least one opening (401) in the heat spreader located in a region of between the two die, an insulator (603) disposed in the at least one opening, and electrically conductive material (1308, 1406) in an insulated hole (705) in the insulator. The heat spreader allows electrical communication between the two die through the opening while the insulator isolates the electrically conductive material and the heat spreader from each other.

Abstract: The dies of a stacked die integrated circuit (IC) employ the address bus to indicate the particular die, or set of dies, targeted by data on a data bus. During manufacture of the stacked die IC, the IC is programmed with information indicating a width of the address bus. During operation, each die addresses the other dies with addresses having the corresponding width based on this programmed information.

Abstract: A first semiconductor device die is provided having a bottom edge incorporating a notch structure that allows sufficient height and width clearance for a wire bond connected to a bond pad on an active surface of a second semiconductor device die upon which the first semiconductor device die is stacked. Use of such notch structures reduces a height of a stack incorporating the first and second semiconductor device die, thereby also reducing a thickness of a semiconductor device package incorporating the stack.

Abstract: An optical die probe wafer testing circuit arrangement and associated testing methodology are described for mounting a production test die (157) and surrounding scribe grid (156) to a test head (155) which is positioned over a wafer (160) in alignment with a die under test (163) and surrounding scribe grid (161, 165), such that one or more optical deflection mirrors (152, 154) in the test head scribe grid (156) are aligned with one or more optical deflection mirrors (162, 164) in the scribe grid (161, 165) for the die under test (163) to enable optical die probe testing on the die under test (163) by directing a first optical test signal (158) from the production test die (157), through the first and second optical deflection mirrors (e.g., 152, 162) and to the first die.

Abstract: The dies of a stacked die IC are tested and, in response to detection of a defect at one of the dies, the type of defect is identified. If the defect is identified as a defective module repairable at the die itself, a redundant module of the die is used to replace the functionality of the defective module. If the defect is identified as one that is not repairable, a replacement die in the die stack is used to replace the functionality of the defective die.

Abstract: An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly.

Abstract: A method of manufacturing a microelectronic assembly (100) and a microelectronic device (4100) that include a stacked structure (101). The stacked structure includes a heat spreader (104), at least one die (106) thermally coupled to at least a portion of one side of the heat spreader, at least one other die (108) thermal coupled to at least a portion of an opposite side of the heat spreader, at least one opening (401) in the heat spreader located in a region of between the two die, an insulator (603) disposed in the at least one opening, and electrically conductive material (1308, 1406) in an insulated hole (705) in the insulator. The heat spreader allows electrical communication between the two die through the opening while the insulator isolates the electrically conductive material and the heat spreader from each other.

Abstract: A high density, low power, high performance information system, method and apparatus are described in which perpendicularly oriented processor and memory die stacks (130, 140, 150, 160, 170) include integrated deflectable MEMS optical beam waveguides (e.g., 190) at each die edge to provide optical communications (182-185) in and between die stacks by supplying deflection voltages to a plurality of deflection electrodes (195-197) positioned on and around each MEMS optical beam waveguide (193-194) to provide two-dimensional alignment and controlled feedback to adjust beam alignment and establish optical communication links between die stacks.

Abstract: A high density, low power, high performance information system, method and apparatus are described in which a laser source (213) on a first die (210) generates a source light beam of unmodulated monochromatic coherent light (281) for distribution via optical beam routing structures (e.g., 214/214a, 224/224a, 234/234a) to a plurality of receiving die (220, 230), each of which includes its own modulator (e.g., 223, 233) for optically receiving at least a portion of the source light beam (281a, 281b) from the first die and generating therefrom an output source light beam of modulated monochromatic coherent light (291, 292) which is encoded at said modulator in response to electrical signal information.

Abstract: A semiconductor device comprising a substrate, a power bus, a heat source circuit, a heat sensitive circuit, and a plurality of electrically and thermally conductive through-silicon-vias (TSVs) in the substrate. The TSVs are electrically coupled to the power bus and positioned between the heat source circuit and the heat sensitive circuit to absorb heat from the heat source circuit.

Abstract: A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (D1-D8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.

Abstract: Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together.

Abstract: A stacked semiconductor device includes a first and second semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the first and second semiconductor devices include active circuitry. The first and second semiconductor devices are stacked so that the first major surface of the first semiconductor device faces the first major surface of the second semiconductor device. At least one continuous conductive via extends from the second major surface of the first semiconductor device to the first major surface of the second semiconductor device. Conductive material fills a cavity adjacent to the contact pad and is in contact with one side of the contact pad. Another side of the contact pad of the first semiconductor device faces and is in contact with another side of the contact pad of the second semiconductor device.