Patents by Inventor Michael Bell

Michael Bell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040219571
    Abstract: A group I intron-derived ribozyme which binds RNA in trans, excises an internal segment from within the RNA, and splices the remaining 5′ and 3′ ends of the RNA back together (the trans-excision-splicing reaction) is disclosed. The excised segment can be as long as 28 nucleotides, or more, and as little as one nucleotide. The ribozymes of the invention are easily modified to alter their sequence specificity. Such ribozymes represent a new and potentially powerful class of generally adaptable genetic therapeutics.
    Type: Application
    Filed: December 9, 2003
    Publication date: November 4, 2004
    Inventors: Stephen M. Testa, Michael A. Bell
  • Patent number: 6691614
    Abstract: A printing sleeve for use in flexographic or gravure printing applications is provided. In particular, the printing sleeve contains a bridge layer that is formed from a generally rigid and relatively expandable material, which is disposed adjacent to a core layer. For example, in one embodiment, the bridge layer is made from a polyurethane material having a Shore D hardness of about 20 to about 85. As a result of the present invention, printing sleeves can be formed to be more durable and maintain better TIR tolerances than conventional printing sleeves.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: February 17, 2004
    Assignee: Rossini North America, Inc.
    Inventors: Michael Bell, Felice Rossini
  • Patent number: 6636265
    Abstract: An inventive method for preventing focus flutter display in a TV receiver or monitor includes the steps of amplifying a received signal for driving cathode elements of a cathode ray tube, and delaying initial full amplification of the signal during the amplifying step for a duration sufficient to prevent focus flutter display on the tube. A corresponding inventive kine driver circuit that prevents display of focus flutter includes an amplifier for amplifying and coupling received video signals to cathode elements of a picture tube, and a control circuit for delaying full amplification of the video signals to be fed to the cathode elements for a duration sufficient to prevent focus flutter display on the tube.
    Type: Grant
    Filed: June 7, 2000
    Date of Patent: October 21, 2003
    Assignee: Thomson Licensing S.A.
    Inventor: Isaac Michael Bell
  • Publication number: 20030069942
    Abstract: The present invention is a process and business of localizing Uniform Resource Identifiers (URI) or Uniform Resource Locators (URL) so to expand the available pool of descriptive domain names that can be registered and to fashion the Internet into an increasingly localized medium. The method would reserve one secondary host name field of a standard number of characters to be dedicated to a locality.
    Type: Application
    Filed: October 7, 2002
    Publication date: April 10, 2003
    Inventor: Jackie Michael Bell
  • Publication number: 20030041212
    Abstract: A caching input/output hub includes a host interface to connect with a host. At least one input/output interface is provided to connect with an input/output device. A write cache manages memory writes initiated by the input/output device. At least one read cache, separate from the write cache, provides a low-latency copy of data that is most likely to be used. The at least one read cache is in communication with the write cache. A cache directory is also provided to track cache lines in the write cache and the at least one read cache. The cache directory is in communication with the write cache and the at least one read cache.
    Type: Application
    Filed: August 27, 2001
    Publication date: February 27, 2003
    Inventors: Kenneth C. Creta, D. Michael Bell, Robert George, Bradford Congdon, Robert Blankenship, Duane January
  • Publication number: 20020078598
    Abstract: A ground engaging portion of an article of footwear for enhancing the traction and flexibility of the ground engaging portion has a plurality of multilevel cleats. The multilevel cleats include a plurality of cleat base elements extending upwardly from a surface thereof to define a first level of the multilevel cleats. A plurality of cleat top elements extend upwardly from a surface of a selected cleat base element to define a second level. The cleat base elements are arranged upon the surface of the ground engaging portion to define both longitudinal and transverse base element grooves therebetween. The cleat top elements are disposed upon a cleat base element to define both longitudinal and transverse top element grooves therebetween.
    Type: Application
    Filed: December 21, 2000
    Publication date: June 27, 2002
    Inventor: Michael Bell
  • Publication number: 20020046668
    Abstract: A printing sleeve for use in flexographic or gravure printing applications is provided. In particular, the printing sleeve contains a bridge layer that is formed from a generally rigid and relatively expandable material, which is disposed adjacent to a core layer. For example, in one embodiment, the bridge layer is made from a polyurethane material having a Shore D hardness of about 20 to about 85. As a result of the present invention, printing sleeves can be formed to be more durable and maintain better TIR tolerances than conventional printing sleeves.
    Type: Application
    Filed: June 15, 2001
    Publication date: April 25, 2002
    Applicant: Rossini North America, Inc. and Erminio Rossini S.p.A.
    Inventors: Michael Bell, Felice Rossini
  • Patent number: 6330630
    Abstract: A bus bridge receives an inbound read request from a master. In response to the read request, the bridge transmits multiple (e.g., two) read request packets to fetch data. The fetched data is stored in the bridge when it returns. When the master returns for its data, the data from each packet is transferred to the master if the data is valid. By issuing two smaller read request packets in response to an inbound read request, inbound read latency is reduced. In addition, if only a single master is being serviced, the system speculatively prefetches data for the master when the master returns to receive its data. Also, if the master is disconnected before completing the data transfer, the data can be subsequently restreamed from the bridge if the data is still valid when the master reconnects.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: December 11, 2001
    Assignee: Intel Corporation
    Inventor: D. Michael Bell
  • Patent number: 6317799
    Abstract: The invention, in one embodiment, is a method for accessing memory. The method includes programming a remote DMA engine from a destination; accessing data in the memory with the DMA engine, the DMA engine operating as programmed by the destination; and transferring the accessed data to the destination.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: November 13, 2001
    Assignee: Intel Corporation
    Inventors: William T. Futral, D. Michael Bell
  • Patent number: 6266778
    Abstract: A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as the skew is distributed over multiple clock periods.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: July 24, 2001
    Assignee: Intel Corporation
    Inventor: D. Michael Bell
  • Patent number: 6154982
    Abstract: A footwear attachment device for releasable mounting on primary footwear, e.g., a boot or shoe, to provide enhanced traction. The primary footwear has an upper including a toe portion and a heel portion, a sole including a fore-foot portion and a heel portion. The attachment device comprising an integral member having been formed of an elastic material and having an upper portion and a sole portion. The sole portion is a generally planar member having a forefoot section, a heel section and a longitudinal axis extending therealong. The upper portion includes a toe-box section and a heel counter section. The toe box section is formed of at least one strip of elastic material and is secured to the forefoot portion of the sole to receive the toe portion of the primary footwear.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: December 5, 2000
    Assignee: Michael Bell
    Inventors: Michael Bell, Jonathan Marc Bell, Eric P. Bell
  • Patent number: 6148356
    Abstract: A computer system includes a host processor coupled to a host bus. A bridge controller is coupled to the host bus and to a plurality of first buses. The computer system also includes one or more bus bridges, each coupled to the bridge controller via one or more of said first buses. Each bus bridge is connected to one or more second buses. Either the first buses or the second buses are each configurable in either an independent mode in which the bus operates independently, or a combined mode in which two or more of said first buses or said second buses are combined to create a single bus.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: November 14, 2000
    Assignee: Intel Corporation
    Inventors: David W. Archer, D. Michael Bell, Doug Moran, Steve Pawlowski
  • Patent number: 6134622
    Abstract: A bus expander bridge is provided for interfacing first and second external buses (such as PCI buses) to a third bus. The bus expander bridge is configurable in either an independent mode in which the first and second external buses operate independently and a combined mode in which the first and second external buses are combined to create a single bus. The bus expander bridge includes a first set of data queues for routing data between the first external bus and the third bus, and a second set of data queues for routing data between the second external bus and the third bus. The bus expander bridge also includes a controller coupled to the first and second sets of data queues and operating the first and second sets of data queues in parallel for the independent mode. The controller routes even addressed data through the first set of data queues and routes odd addressed data through the second set of data queues for the combined mode.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: October 17, 2000
    Assignee: Intel Corporation
    Inventors: Suvansh Kapur, Kevin Koschoreck, Srinand Venkatesan, D. Michael Bell
  • Patent number: 6108736
    Abstract: A system and method for controlling the flow of information between devices. A count is maintained representative of requests issued by a first device. The count is incremented for each packet issued by a first device and decremented for each packet received at the first device. A maximum buffer count, which corresponds to the capacity of the buffer is used to perform flow control by determining when the maximum buffer count is to be exceeded by the issuance of a packet by the first device. If the count is to be exceed, issuance of packets by the first device is prevented until the maximum buffer count will not be exceeded by issuance of the packet.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: August 22, 2000
    Assignee: Intel Corporation
    Inventor: D. Michael Bell
  • Patent number: 6088370
    Abstract: A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as the skew is distributed over multiple clock periods.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: July 11, 2000
    Assignee: Intel Corporation
    Inventor: D. Michael Bell
  • Patent number: 6081851
    Abstract: The invention, in one embodiment, is a method for accessing memory. The method includes programming a remote DMA engine from a destination; accessing data in the memory with the DMA engine, the DMA engine operating as programmed by the destination; and transferring the accessed data to the destination.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: June 27, 2000
    Assignee: Intel Corporation
    Inventors: William T. Futral, D. Michael Bell
  • Patent number: 6070207
    Abstract: A computer system includes a host processor coupled to a host bus. The computer system also includes a memory system coupled to the host bus, and an I/O bridge controller coupled to the host bus and including a plurality of ports. An I/O bus bridge is provided that is hot plug connectable to at least one of the bridge controller ports via one or more first buses. There are one or more second buses coupled to the I/O bus bridge.
    Type: Grant
    Filed: August 20, 1998
    Date of Patent: May 30, 2000
    Assignee: Intel Corporation
    Inventor: D. Michael Bell
  • Patent number: 6047120
    Abstract: The dual mode bus bridge accommodates either two 64-bit personal computer interface (PCI) buses or four 32-bit PCI buses. In either case, only a single load is applied to the host bus. The dual mode bridge includes a bridge controller unit connected to a pair of expansion bridge units by respective internal buses. Each expansion bridge unit includes two sets of 64-bit wide queues and buffers. For 32-bit PCI operation, the two sets of queues and buffers are operated in parallel. For 64-bit PCI operation, the two sets of queues and buffers are linked together so as to appear in series to provide a single queue structure having twice the depth of the separate queue structures for a 32-bit mode operation. As such, undue duplication of queue and buffer resources is avoided. Method and apparatus embodiments of the invention are described.
    Type: Grant
    Filed: September 9, 1998
    Date of Patent: April 4, 2000
    Assignee: Intel Corporation
    Inventor: D. Michael Bell
  • Patent number: 6021451
    Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: February 1, 2000
    Assignee: Intel Corporation
    Inventors: D. Michael Bell, Mark A. Gonzales, Susan S. Meredith
  • Patent number: 6006860
    Abstract: A harness or belt to be worn by a person connected to some elevated anchor point, e.g., a rope grab on a safety line, to prevent the person from a fall. The device comprises at least one web or strap of a fabric which is subject to a shock load when the device has been used to arrest the fall of the person and plural shock load indicating strands or fibers located on the web or strap. The web or strap is a generally flat member having an exterior surface and is formed of plural interlaced strands of a first stretchable, yet strong material, e.g., nylon or polyester. The shock load indicating strands are of a contrasting color to the strands forming the strap or web and are visible from the exterior surface of the web. The shock load indicating strands are of a lesser stretchability than the strands of the web or strap.
    Type: Grant
    Filed: October 20, 1994
    Date of Patent: December 28, 1999
    Inventor: Michael Bell