Patents by Inventor Michael Billeci
Michael Billeci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9792124Abstract: Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.Type: GrantFiled: February 13, 2015Date of Patent: October 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Billeci, James J. Bonanno, Adam B. Collura, Christian Jacobi, Anthony Saporito, Timothy J. Slegel
-
Patent number: 9720764Abstract: Uncorrectable memory errors in pipelined central processing units. A processor core may be connected to a memory system and it may include a processor cache. In response to determining an uncorrectable error in data stored in the memory system, the address of a memory location of the uncorrectable error is stored in an address buffer and a recovery procedure is performed for the processor core. When fetching data from a memory location and if it is determined that the address of this memory location is stored in the address buffer, the content of a cache line related to the address is moved into a quarantine buffer of the processor core. When detecting an error in the data of the moved cache line, a repair procedure for the data of this address is triggered.Type: GrantFiled: July 30, 2015Date of Patent: August 1, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Billeci, Uwe Brandt, Christian Jacobi, Martin Recktenwald
-
Patent number: 9665376Abstract: In one embodiment, a computer-implemented method includes requesting, by a first processor thread of a computer processor, access to exception tracking logic. The exception tracking logic is accessible by a plurality of processor threads. The first processor thread receives access to the exception tracking logic. The first processor thread executes a process in slow mode. Based on detecting an exception in slow mode, the first processor thread stores, in the exception tracking logic, exception information about the exception. The exception information is copied from the exception tracking logic to a set of external registers outside the exception tracking logic. The exception tracking logic is released to allow access to the exception tracking logic by other processor threads of the plurality of processor threads.Type: GrantFiled: December 15, 2014Date of Patent: May 30, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Khary J. Alexander, Michael Billeci, Fadi Y. Busaba, Mark S. Farrell, Christian Jacobi, Timothy J. Slegel
-
Patent number: 9619237Abstract: Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.Type: GrantFiled: August 23, 2016Date of Patent: April 11, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Billeci, James J. Bonanno, Adam B. Collura, Christian Jacobi, Anthony Saporito, Timothy J. Slegel
-
Publication number: 20160350125Abstract: Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.Type: ApplicationFiled: August 23, 2016Publication date: December 1, 2016Inventors: Michael Billeci, James J. Bonanno, Adam B. Collura, Christian Jacobi, Anthony Saporito, Timothy J. Slegel
-
Patent number: 9507602Abstract: In one embodiment, a computer-implemented method includes requesting, by a first processor thread of a computer processor, access to exception tracking logic. The exception tracking logic is accessible by a plurality of processor threads. The first processor thread receives access to the exception tracking logic. The first processor thread executes a process in slow mode. Based on detecting an exception in slow mode, the first processor thread stores, in the exception tracking logic, exception information about the exception. The exception information is copied from the exception tracking logic to a set of external registers outside the exception tracking logic. The exception tracking logic is released to allow access to the exception tracking logic by other processor threads of the plurality of processor threads.Type: GrantFiled: March 28, 2016Date of Patent: November 29, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Khary J. Alexander, Michael Billeci, Fadi Y. Busaba, Mark S. Farrell, Christian Jacobi, Timothy J. Slegel
-
Patent number: 9454377Abstract: Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.Type: GrantFiled: February 24, 2016Date of Patent: September 27, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Billeci, James J. Bonanno, Adam B. Collura, Christian Jacobi, Anthony Saporito, Timothy J. Siegel
-
Publication number: 20160239310Abstract: Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.Type: ApplicationFiled: February 24, 2016Publication date: August 18, 2016Inventors: Michael Billeci, James J. Bonanno, Adam B. Collura, Christian Jacobi, Anthony Saporito, Timothy J. Slegel
-
Publication number: 20160239301Abstract: Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.Type: ApplicationFiled: February 13, 2015Publication date: August 18, 2016Inventors: Michael Billeci, James J. Bonanno, Adam B. Collura, Christian Jacobi, Anthony Saporito, Timothy J. Slegel
-
Publication number: 20160196144Abstract: In one embodiment, a computer-implemented method includes requesting, by a first processor thread of a computer processor, access to exception tracking logic. The exception tracking logic is accessible by two or more processor threads. The first processor thread receives access to the exception tracking logic. The first processor thread executes a process in slow mode. Based on detecting an exception in slow mode, the first processor thread stores, in the exception tracking logic, exception information about the exception. The exception information is copied from the exception tracking logic to a set of external registers outside the exception tracking logic. The exception tracking logic is released to allow access to the exception tracking logic by other processor threads of the two or more processor threads.Type: ApplicationFiled: March 28, 2016Publication date: July 7, 2016Inventors: Khary J. Alexander, Michael Billeci, Fadi Y. Busaba, Mark S. Farrell, Christian Jacobi, Timothy J. Slegel
-
Publication number: 20160170768Abstract: In one embodiment, a computer-implemented method includes requesting, by a first processor thread of a computer processor, access to exception tracking logic. The exception tracking logic is accessible by two or more processor threads. The first processor thread receives access to the exception tracking logic. The first processor thread executes a process in slow mode. Based on detecting an exception in slow mode, the first processor thread stores, in the exception tracking logic, exception information about the exception. The exception information is copied from the exception tracking logic to a set of external registers outside the exception tracking logic. The exception tracking logic is released to allow access to the exception tracking logic by other processor threads of the two or more processor threads.Type: ApplicationFiled: December 15, 2014Publication date: June 16, 2016Inventors: Khary J. Alexander, Michael Billeci, Fadi Y. Busaba, Mark S. Farrell, Christian Jacobi, Timothy J. Slegel
-
Patent number: 9323640Abstract: Disclosed are a method and system for measuring the performance of individual logical partitions of a logically partitioned computer system. Preferably, the method and system both hardware and firmware to allow measurement samples to be collected only for user specified zones of interest. In one embodiment, the method comprises the steps of specifying a Zone or Zones of interest (a Zone being a logical partition), collecting measurement samples only from the one or more specified Zones of interest, and measuring the performance of each of these Zones using only the measurement samples collected from said each of the Zones.Type: GrantFiled: June 7, 2012Date of Patent: April 26, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jane H. Bartik, Michael Billeci, Lisa C. Heller, Donald G. O'Brien, Bruce A. Wagar, Patrick M. West, Jr.
-
Publication number: 20160034336Abstract: Uncorrectable memory errors in pipelined central processing units. A processor core may be connected to a memory system and it may include a processor cache. In response to determining an uncorrectable error in data stored in the memory system, the address of a memory location of the uncorrectable error is stored in an address buffer and a recovery procedure is performed for the processor core. When fetching data from a memory location and if it is determined that the address of this memory location is stored in the address buffer, the content of a cache line related to the address is moved into a quarantine buffer of the processor core. When detecting an error in the data of the moved cache line, a repair procedure for the data of this address is triggered.Type: ApplicationFiled: July 30, 2015Publication date: February 4, 2016Inventors: Michael Billeci, Uwe Brandt, Christian Jacobi, Martin Recktenwald
-
Patent number: 9075600Abstract: A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.Type: GrantFiled: June 24, 2010Date of Patent: July 7, 2015Assignee: International Business Machines CorporationInventors: Gregory W. Alexander, Brian D. Barrick, Michael Billeci, Fadi Y. Busaba, Bruce C. Giamei, David A. Schroter
-
Patent number: 8683180Abstract: A method, processor, and computer program product employing an intermediate register mapper within a register renaming mechanism. A logical register lookup determines whether a hit to a logical register associated with the dispatched instruction has occurred. In this regard, the logical register lookup searches within at least one register mapper from a group of register mappers, including an architected register mapper, a unified main mapper, and an intermediate register mapper. A single hit to the logical register is selected among the group of register mappers. If an instruction having a mapper entry in the unified main mapper has finished but has not completed, the mapping contents of the register mapper entry in the unified main mapper are moved to the intermediate register mapper, and the unified register mapper entry is released, thus increasing a number of unified main mapper entries available for reuse.Type: GrantFiled: October 13, 2009Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: Brian D. Barrick, Michael Billeci, Lee E. Eisen
-
Patent number: 8516228Abstract: A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.Type: GrantFiled: March 19, 2008Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Khary J. Alexander, Michael Billeci, Fadi Y. Busaba, Bruce C. Giamei
-
Patent number: 8453124Abstract: A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.Type: GrantFiled: December 23, 2009Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Gregory W. Alexander, Jane Bartik, Michael Billeci, David Hutton, Christian Jacobi, Jang-Soo Lee, Eric Schwarz, Chung-Lung Shum, Phil C. Yeh
-
Publication number: 20120246439Abstract: Disclosed are a method and system for measuring the performance of individual logical partitions of a logically partitioned computer system. Preferably, the method and system both hardware and firmware to allow measurement samples to be collected only for user specified zones of interest. In one embodiment, the method comprises the steps of specifying a Zone or Zones of interest (a Zone being a logical partition), collecting measurement samples only from the one or more specified Zones of interest, and measuring the performance of each of these Zones using only the measurement samples collected from said each of the Zones.Type: ApplicationFiled: June 7, 2012Publication date: September 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jane H. Bartik, Michael Billeci, Lisa C. Heller, Donald G. O'Brien, Bruce A. Wagar, Patrick M. West, JR.
-
Patent number: 8209668Abstract: Disclosed are a method and system for measuring the performance of individual logical partitions of a logically partitioned computer system. Preferably, the method and system both hardware and firmware to allow measurement samples to be collected only for user specified zones of interest. In one embodiment, the method comprises the steps of specifying a Zone or Zones of interest (a Zone being a logical partition), collecting measurement samples only from the one or more specified Zones of interest, and measuring the performance of each of these Zones using only the measurement samples collected from said each of the Zones.Type: GrantFiled: August 30, 2006Date of Patent: June 26, 2012Assignee: International Business Machines CorporationInventors: Jane H. Bartik, Michael Billeci, Lisa C. Heller, Donald G O'Brien, Bruce Wagar, Patrick M. West, Jr.
-
Patent number: 8201067Abstract: A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.Type: GrantFiled: February 25, 2008Date of Patent: June 12, 2012Assignee: International Business Machines CorporationInventors: Fadi Y. Busaba, Khary J. Alexander, Michael Billeci, Bruce C. Giamei, Vimal M. Kapadia