Abstract: A method and apparatus for operating a clock in a processor having asymmetrically mirrored base-mirror units is disclosed. The method includes initializing a base-unit and a mirror-unit of the processor to the same state, and starting the mirror-unit-clock one clock cycle later than the base-unit-clock.

Abstract: An embodiment of the invention is a multiprocessor system for detecting and recovering from errors. The multiprocessor system includes a first processor and a second processor. The first processor detects an error and initiates a recovery process. The first processor and said second processor synchronize at least one recovery action during the recovery process.

Abstract: A processor responsive to a clock cycle includes a base-unit, a mirror-unit that is a duplicate instance of the base-unit, a non-duplicate-unit in signal communication with the base and mirror units, a first staging register disposed at the input to the mirror-unit for delaying the input signal thereto by at least one clock cycle, and a second staging register disposed at the output of the mirror-unit for delaying the output signal therefrom by at least one clock cycle. The non-duplicate-unit includes a comparator for comparing the output signals of the base and mirror units.

Abstract: A system for controlling asynchronous updates to a register, the system including a generally accessible register that is asynchronously updateable by hardware and software. The system also includes protection logic that is in communication with the register. The protection logic includes circuitry to prevent a hardware update to the register from being overwritten by a software update.

Abstract: An embodiment of the invention is a method for capturing hardware trace data. A wrap-back address space is defined and during compression mode, trace data is circularly stored in the wrap-back address space. Upon exiting compression mode, a write address is established for further trace data such that trace data prior to existing compression mode is maintained.

Abstract: A method and apparatus for operating a clock in a processor having asymmetrically mirrored base-mirror units is disclosed. The method includes initializing a base-unit and a mirror-unit of the processor to the same state, and starting the mirror-unit-clock one clock cycle later than the base-unit-clock.

Abstract: An embodiment of the invention is a multiprocessor system for detecting and recovering from errors. The multiprocessor system includes a first processor and a second processor. The first processor detects an error and initiates a recovery process. The first processor and said second processor synchronize at least one recovery action during the recovery process.

Abstract: A processor responsive to a clock cycle includes a base-unit, a mirror-unit that is a duplicate instance of the base-unit, a non-duplicate-unit in signal communication with the base and mirror units, a first staging register disposed at the input to the mirror-unit for delaying the input signal thereto by at least one clock cycle, and a second staging register disposed at the output of the mirror-unit for delaying the output signal therefrom by at least one clock cycle. The non-duplicate-unit includes a comparator for comparing the output signals of the base and mirror units.