Abstract: In one implementation, a switching circuit includes a pass switch including group III-V, for example III-Nitride, transistors coupled between an input of the switching circuit and an output of the switching circuit. The switching circuit further includes a shunt switch configured to ground the input of the switching circuit while the pass switch is disabled. The switching circuit also includes a gate control transistor configured to reduce resistance between a control terminal of the pass switch and/or the shunt switch and gate of the group III-V transistor of the pass switch and/or the shunt switch so as to enable and disable the pass switch and/or shunt switch. The gate control transistor can be coupled across a gate resistor of the pass switch and/or the shunt switch. The gate control transistor can reduce the resistance in order to lower the OFF state impedance of the pass switch and/or the shunt switch.

Abstract: In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.

Abstract: In an exemplary implementation, a semiconductor device includes a drain pad on a semiconductor substrate, the drain pad being coupled to a plurality of drain fingers. The semiconductor device further includes a source pad on the semiconductor substrate, the source pad being coupled to a plurality of source fingers. The plurality of source fingers is interdigitated with the plurality of drain fingers. Furthermore, an outer corner of the drain pad has a gradual transition between adjoining sides of the drain pad. The gradual transition between the adjoining sides of the drain pad reduces a termination electric field at the outer corner of the drain pad. Furthermore, the gradual transition between the adjoining sides of the drain pad increases the breakdown voltage of the semiconductor device.

Abstract: A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer.

Abstract: There are disclosed herein various implementations of an integrated half-bridge circuit with low side and high side composite switches. In one exemplary implementation, such an integrated half-bridge circuit includes a III-N body including first and second III-N field-effect transistors (FETs) monolithically integrated with and situated over a first group IV FET. The integrated half-bridge circuit also includes a second group IV FET stacked over the III-N body. The first group IV FET is cascoded with the first III-N FET to provide one of the low side and the high side composite switches, and the second group IV FET is cascoded with the second III-N FET to provide the other of the low side and the high side composite switches.

Abstract: There are disclosed herein various implementations of a short circuit protected composite switch and a circuit including such a switch. In one exemplary implementation, such a short circuit protected composite switch includes a III-N field-effect transistor (FET) having a drain, a source, and a gate, and a high current group IV FET coupled in series with the III-N FET and configured to limit a current through the III-N FET. The short circuit protected composite switch also includes another group IV FET coupled between the gate and the source of the III-N FET, and another transistor coupled between the gate of the III-N FET and a source of the high current group IV FET.

Abstract: A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.

Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.

Abstract: A method that includes implantation of dopants while a III-nitride body is being grown on a substrate, and an apparatus for the practice of the method.

Abstract: A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N+ III-Nitride pad layers and the gate may be a Schottky gate or an insulated gate.

Abstract: A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die.

Abstract: There are disclosed herein various implementations of semiconductor structures including high resistivity substrates. In one exemplary implementation, such a semiconductor structure includes a substrate having a resistivity of greater than or approximately equal to one kiloohm-centimeter (1 k?-cm), and a III-N high electron mobility transistor (HEMT) having a drain, a source, and a gate, fabricated over the substrate. The III-N HEMT is configured to produce a two-dimensional electron gas (2 DEG). The resistivity of the substrate reduces the capacitive coupling of the 2 DEG to the substrate. In one implementations, a spatially confined dielectric region is formed in the substrate, under at least one of the drain and the source.

Abstract: There are disclosed herein various implementations of semiconductor structures including one or more spatially confined dielectric regions. In one exemplary implementation, such a semiconductor structure includes a III-Nitride field-effect transistor (FET) having a drain, a source, and a gate, fabricated over a substrate. A spatially confined dielectric region is formed under the drain in the substrate, the spatially confined dielectric region reducing a capacitive coupling of the drain to the substrate. In another exemplary implementation, a spatially confined dielectric region is formed under each of the source and the drain of the FET, in the substrate, the spatially confined dielectric regions reducing a capacitive coupling of the source and the drain to the substrate.

Abstract: Disclosed is a buck converter for converting a high voltage at the input of the buck converter to a low voltage at the output of the buck converter. The buck converter includes a control circuitry configured to control a duty cycle of a control switch, the control switch being interposed between the input and the output of the buck converter. A synchronous switch is interposed between the output and ground. The control switch and the synchronous switch comprise depletion-mode III-nitride transistors. In one embodiment, at least one of the control switch and the synchronous switches comprises a depletion-mode GaN HEMT. The buck converter further includes protection circuitry configured to disable current conduction through the control switch while the control circuitry is not powered up.

Abstract: In an exemplary implementation, an integrated assembly includes a printed circuit board, and a depletion mode III-Nitride transistor die and a group IV transistor die coupled to the printed circuit board. The depletion mode III-Nitride transistor die is situated on one side of the printed circuit board and the group IV transistor die is situated on an opposing side of the printed circuit board. At least one via in the printed circuit board electrically connects the depletion mode III-Nitride transistor die to the group IV transistor die. In some implementations, the depletion mode III-Nitride transistor die is in cascode with the group IV transistor die. Furthermore, the depletion mode III-Nitride transistor die can he situated over the group IV transistor die.

Abstract: In an exemplary implementation, a semiconductor device includes a III-nitride heterojunction including a III-nitride barrier layer situated over a III-nitride channel layer to form a conduction channel including a two-dimensional electron gas. The semiconductor device further includes a gate electrode coupled to a field plate. The field plate includes a plurality of steps insulated from the conduction channel by a dielectric body and the III-nitride barrier layer. The dielectric body under each one of the plurality of steps contributes to a breakdown voltage that is at least twice a breakdown voltage of the semiconductor device at each corresponding step. The breakdown voltage can correspond to a breakdown voltage of the dielectric body and the III-nitride barrier layer.

Abstract: There are disclosed herein various implementations of a method and system for ion implantation at high temperature surface equilibrium conditions. The method may include situating a III-Nitride semiconductor body in a surface equilibrium chamber, establishing a gas pressure greater than or approximately equal to a surface equilibrium pressure of the III-Nitride semiconductor body, and heating the III-Nitride semiconductor body to an elevated implantation temperature in the surface equilibrium chamber while substantially maintaining the gas pressure. The method also includes implanting the III-Nitride semiconductor body in the surface equilibrium at the elevated implantation temperature chamber while substantially maintaining the gas pressure, the implanting being performed using an ion implanter interfacing with the surface equilibrium chamber.

Abstract: A III-nitride semiconductor device which includes a charged gate insulation body.

Abstract: In one implementation, a method of forming a P type III-nitride material includes forming a getter material over a III-nitride material, the III-nitride material having residual complexes formed from P type dopants and carrier gas impurities. The method further includes gettering at least some of the carrier gas impurities, from at least some of the residual complexes, into the getter material to form the P type III-nitride material. In some implementations, the carrier gas impurities include hydrogen and the getter material includes at least partially titanium. An overlying material can be formed on the getter material prior to gettering at least some of the carrier gas impurities.

Abstract: A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.