Abstract: In one implementation, an integrated power stage includes a common die situated over a load stage, the common die includes a driver stage and power switches. The power switches include a control transistor and a sync transistor. A drain of the control transistor receives an input voltage of the common die on one side (e.g., on a top surface) of the common die. A source of the control transistor is coupled to a drain of the sync transistor and provides an output voltage of the common die on an opposite side (e.g., on a bottom surface) of the common die. An interposer may be included under the power stage and includes an output inductor and optionally an output capacitor coupled to the output voltage of the common die on the opposite side of the common die.

Abstract: In one implementation, a stacked composite device comprises a group IV diode and a group III-V transistor stacked over the group IV diode. A cathode of the group IV diode is in contact with a source of the group III-V transistor, an anode of the group IV diode is coupled to a gate of the group III-V transistor to provide a composite anode on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite cathode on a top side of the stacked composite device.

Abstract: In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.

Abstract: In one implementation, a stacked composite device comprises a group IV vertical transistor and a group III-V transistor stacked over the group IV vertical transistor. A drain of the group IV vertical transistor is in contact with a source of the group III-V transistor, a source of the group IV vertical transistor is coupled to a gate of the group III-V transistor to provide a composite source on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on a top side of the stacked composite device. A gate of the group IV vertical transistor provides a composite gate on the top side of the stacked composite device.

Abstract: There are disclosed herein various implementations of semiconductor devices having passive oscillation control. In one exemplary implementation, such a device is implemented to include a III-nitride transistor having a source electrode, a gate electrode and a drain electrode. A damping resistor is configured to provide the passive oscillation control for the III-nitride transistor. In one implementation, the damping resistor includes at least one lumped resistor.

Abstract: According to one exemplary embodiment, a rectifier circuit includes a diode. A first depletion-mode transistor is connected to a cathode of the diode. Also, at least one second depletion-mode transistor is in parallel with the first depletion-mode transistor and is configured to supply a pre-determined current range to a cathode of the diode. A pinch off voltage of the at least one second depletion-mode transistor can be more negative than a pinch off voltage of the first depletion-mode transistor and the at least one second depletion-mode transistor can be configured to supply the pre-determined current range while the first depletion-mode transistor is OFF. Also, the pre-determined current range can be greater than a leakage current of the first depletion-mode transistor.

Abstract: An interposer electrical interface for placing a DC-DC converter in close proximity with an IC powered by the converter, the DC-DC converter including at least one switching node power supply stage, the at least one switching node power supply stage providing regulated power to the IC, the close proximity of the DC-DC converter and IC allowing for high efficiency in provision of the regulated power from the DC-DC converter to the IC, the interposer electrical interface comprising at least one electrical energy storage element.

Abstract: A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.

Abstract: There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure.

Abstract: A III-nitride semiconductor device which includes a charged gate insulation body.

Abstract: In accordance with one implementation of the present disclosure, a III-Nitride heterojunction device includes a III-Nitride channel layer, a III-Nitride multilayer spacer situated over the III-Nitride channel layer, and a III-Nitride barrier layer situated over the III-Nitride multilayer spacer. A two-dimensional electron gas (2DEG) is formed near an interface of said III-Nitride Channel layer and said III-Nitride multilayer spacer. The III-Nitride multilayer spacer includes a III-Nitride interlayer. In one implementation, the III-Nitride multilayer spacer includes a III-Nitride polarization layer that is situated over the III-Nitride interlayer. The III-Nitride polarization layer has a higher total polarization than the III-Nitride interlayer, the III-Nitride channel layer, and the III-Nitride barrier layer.

Abstract: A III-nitride semiconductor device which includes a charged gate insulation body.

Abstract: A III-nitride power device that includes a Schottky electrode surrounding one of the power electrodes of the device.

Abstract: A III-nitride semiconductor device which includes a charged floating gate electrode.

Abstract: A III-nitride device having a support substrate that may include a first silicon body, a second silicon body, an insulation body interposed between the first and second silicon bodies, and a III-nitride body formed over the second silicon body.

Abstract: A power arrangement that includes a monolithically integrated III-nitride power stage having III-nitride power switches and III-nitride driver switches.

Abstract: An integrated circuit that includes a power stage and a driver stage, all stages using III-nitride power devices.

Abstract: A power converter driver that is supplied with two different voltages.

Abstract: In one embodiment a method enabling in situ dopant implantation during growth of a III-nitride semiconductor body, comprises establishing a growth environment for the III-nitride semiconductor body in a composite III-nitride chamber having a dopant implanter and a growth chamber, growing the III-nitride semiconductor body in the growth chamber, and implanting the III-nitride semiconductor body in situ in the growth chamber using the dopant implanter. A semiconductor device produced using the disclosed method comprises a III-nitride semiconductor body having a first conductivity type formed over a support substrate, and at least one doped region produced by in situ dopant implantation of the III-nitride semiconductor body during its growth, that at least one doped region having a second conductivity type.

Abstract: A III-nitride semiconductor device which includes a charged floating gate electrode.