Patents by Inventor Michael Brunolli
Michael Brunolli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10613613Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.Type: GrantFiled: January 5, 2018Date of Patent: April 7, 2020Assignee: QUALCOMM IncorporatedInventors: Michael Brunolli, Stephen Thilenius, Patrick Isakanian, Vaishnav Srinivas
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Patent number: 10461643Abstract: A system and method are provided for supplying bulk current to a voltage regulator embedded on a system-on-chip (SoC). An embedded voltage regulator (EVR) supplies a regulated voltage to a functional unit, the current demand is determined, and a current control signal is generated. An off-SoC bulk current source accepts the current control signal and supplies auxiliary (bulk) current to the functional unit in response to the current control signal. For example, in a first period of time a dynamic increase demand for a first current. Initially the EVR supplies the first current and creates an increase in SoC thermal loading. Subsequently, the EVR supplies a current less than the first current while the bulk current source supplies the bulk of the current. As a result, the bulk current source creates an off-SoC thermal load.Type: GrantFiled: April 4, 2019Date of Patent: October 29, 2019Assignee: nanoHenry, Inc.Inventor: Michael Brunolli
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Publication number: 20190312515Abstract: A system and method are provided for supplying bulk current to a voltage regulator embedded on a system-on-chip (SoC). An embedded voltage regulator (EVR) supplies a regulated voltage to a functional unit, the current demand is determined, and a current control signal is generated. An off-SoC bulk current source accepts the current control signal and supplies auxiliary (bulk) current to the functional unit in response to the current control signal. For example, in a first period of time a dynamic increase demand for a first current. Initially the EVR supplies the first current and creates an increase in SoC thermal loading. Subsequently, the EVR supplies a current less than the first current while the bulk current source supplies the bulk of the current. As a result, the bulk current source creates an off-SoC thermal load.Type: ApplicationFiled: April 4, 2019Publication date: October 10, 2019Inventor: Michael Brunolli
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Patent number: 10169262Abstract: Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command clock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.Type: GrantFiled: July 7, 2016Date of Patent: January 1, 2019Assignee: QUALCOMM IncorporatedInventors: David West, Vaishnav Srinivas, Michael Brunolli, Jungwon Suh
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Publication number: 20180211957Abstract: A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.Type: ApplicationFiled: March 21, 2018Publication date: July 26, 2018Inventors: Seid Hadi RASOULI, Michael BRUNOLLI, Christine HAU-RIEGE, Mickael Sebtastien Alain MALABRY, Sucheta Kumar HARISH, Prathiba BALASUBRAMANIAN, Kamesh MEDISETTI, Nikolay BOMSHTEIN, Animesh DATTA, Ohsang KWON
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Publication number: 20180129267Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.Type: ApplicationFiled: January 5, 2018Publication date: May 10, 2018Inventors: Michael BRUNOLLI, Stephen THILENIUS, Patrick ISAKANIAN, Vaishnav Srinivas
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Patent number: 9910482Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.Type: GrantFiled: September 24, 2015Date of Patent: March 6, 2018Assignee: QUALCOMM IncorporatedInventors: Michael Brunolli, Stephen Thilenius, Patrick Isakanian, Vaishnav Srinivas
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Patent number: 9871012Abstract: Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.Type: GrantFiled: March 14, 2013Date of Patent: January 16, 2018Assignee: QUALCOMM IncorporatedInventors: Vaishnav Srinivas, Bernie Jord Yang, Michael Brunolli, David Ian West, Charles David Paynter
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Publication number: 20170090546Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.Type: ApplicationFiled: September 24, 2015Publication date: March 30, 2017Inventors: Michael Brunolli, Stephen Thilenius, Patrick Isakanian, Vaishnav Srinivas
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Publication number: 20170017587Abstract: Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command dock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.Type: ApplicationFiled: July 7, 2016Publication date: January 19, 2017Inventors: David West, Vaishnav Srinivas, Michael Brunolli, Jungwon Suh
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Patent number: 9083176Abstract: In a particular embodiment, a circuit includes a power supply, a ground, and a clamping transistor circuit coupled to the power supply and to the ground. The circuit further includes a disable clamp circuit. The disable clamp circuit is coupled to the power supply and is responsive to a second power supply input to selectively disable the clamping transistor circuit by modifying a charging current applied to a capacitor of the clamping transistor circuit. In a particular embodiment, modifying the charging current includes enabling a second charging path. Enabling the second charging path enables charging the capacitor at a higher charging rate than a charging rate associated with charging the capacitor via a first charging path.Type: GrantFiled: January 11, 2013Date of Patent: July 14, 2015Assignee: QUALCOMM IncorporatedInventors: Eugene Robert Worley, Sreeker Dundigal, Evan Siansuri, Reza Jalilizeinali, Michael Brunolli
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Publication number: 20150109030Abstract: An output driver configured to drive an output node includes a pull-down section having a plurality of legs and a pull-up section having a plurality of pull-up legs. Each leg and pull-up leg includes a data path and a calibration path. The data paths in the pull-down section are configured to conduct to ground responsive to an assertion of a complement data output signal whereas the data paths in the pull-up section are configured to conduct to a power supply node responsive to a de-assertion of the complement data output signal.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Applicant: QUALCOMM IncorporatedInventors: Michael Brunolli, Mark Wayland
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Publication number: 20150109023Abstract: An output driver for driving a data output signal through an output pad includes a plurality of calibration paths to calibrate the impedance of the output pad. Depending upon the desired impedance, various ones of the calibration paths are selectively coupled to the output pad. Each selected calibration path adds a capacitive load to a data node, which affects the slew rate for the data output signal. To adjust the capacitive load on the data node in light of the calibration path selections, the output driver includes a plurality of selectable capacitors corresponding to the plurality of calibration paths. If a calibration path is not selected to couple to the output pad, the corresponding selectable capacitor capacitively loads the data node.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Applicant: QUALCOMM IncorporatedInventors: Michael Brunolli, Mark Wayland
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Publication number: 20150042401Abstract: An input receiver includes a first pass transistor coupled between an input pad and an internal receiver node. The first pass transistor includes a controlled floating gate capacitively coupled to the input pad. A source follower transistor couples between the internal receiver node and a power supply. A gate for the source follower transistor couples to the input pad.Type: ApplicationFiled: August 8, 2013Publication date: February 12, 2015Applicant: QUALCOMM INCORPORATEDInventors: Stephen Knol, Michael Brunolli, Chiew-Guan Tan, Damen Redelings
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Patent number: 8893063Abstract: A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools.Type: GrantFiled: April 9, 2013Date of Patent: November 18, 2014Assignee: QUALCOMM IncorporatedInventors: Behnam Malek-Khosravi, Michael Brunolli
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Publication number: 20140198414Abstract: In a particular embodiment, a circuit includes a power supply, a ground, and a clamping transistor circuit coupled to the power supply and to the ground. The circuit further includes a disable clamp circuit. The disable clamp circuit is coupled to the power supply and is responsive to a second power supply input to selectively disable the clamping transistor circuit by modifying a charging current applied to a capacitor of the clamping transistor circuit. In a particular embodiment, modifying the charging current includes enabling a second charging path. Enabling the second charging path enables charging the capacitor at a higher charging rate than a charging rate associated with charging the capacitor via a first charging path.Type: ApplicationFiled: January 11, 2013Publication date: July 17, 2014Applicant: QUALCOMM IncorporatedInventors: Eugene Robert Worley, Sreeker Dundigal, Evan Siansuri, Reza Jalilizeinali, Michael Brunolli
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Publication number: 20140061642Abstract: Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.Type: ApplicationFiled: March 14, 2013Publication date: March 6, 2014Applicant: QUALCOMM IncorporatedInventors: Vaishnav Srinivas, Bernie Jord Yang, Michael Brunolli, David Ian West, Charles David Paynter
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Patent number: 8423930Abstract: A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools.Type: GrantFiled: April 5, 2010Date of Patent: April 16, 2013Assignee: QUALCOMM IncorporatedInventors: Behnam Malek-Khosravi, Michael Brunolli
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Patent number: 7802216Abstract: A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools.Type: GrantFiled: September 13, 2007Date of Patent: September 21, 2010Assignee: Rapid Bridge LLCInventors: Behnam Malek-Khosravi, Michael Brunolli
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Publication number: 20100188060Abstract: A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools.Type: ApplicationFiled: April 5, 2010Publication date: July 29, 2010Inventors: Behnam Malek-Khosravi, Michael Brunolli