Abstract: In a data processing system, a method for performing register renaming with back-up capability. A register renaming apparatus (18) comprises a logical-physical (LP) register map (30), a free list (32), and an internal swap bus (90) for exchanging information between the two. The register renaming hardware (18) is connected to an instruction sequencer (12) and instruction decode/issue logic (16). Each time the decode/issue logic (16) decodes an instruction(s), the logical registers to be read index the LP map (30) to find the physical register "name" where their values can be found. The free list 32 is indexed by instruction slot numbers. Each free list cell (60-75) contains two physical register names a "last" and a "current", as well as pointer (80-83) designating which name is "current". As each write is done the "current" name is transferred to the LP map 30, and the previous physical register name in the LP map (30) is installed in the free list (32) in the place of the "last" name.