Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: According to an embodiment, a content addressable memory (CAM) device (104) may be capable of executing a “restricted” search operation. A restricted search operation (an “explore” or “search beyond” operation) may compare only a portion of the CAM entries to a search key device. Preferably, a restricted search operation may restrict searches to entries having an index value greater than a received search index value.

Abstract: A voltage regulation scheme for an on-chip voltage generator includes a voltage sensing circuit (VSC) and a configurable buffer circuit (CBC) to regulate the on-chip voltage generator. The CBC generates an output signal that is received by the on-chip voltage generator to activate and de-activate the voltage generator. The VSC generates a voltage level detection (VLD) signal having a voltage level that is a function of the level of the on-chip generated voltage. The CBC receives a control signal that is used to dynamically configure the chip into an operational mode, as well as the VLD signal. In response to the control signal, the switch threshold of the CBC is configured to a predetermined level corresponding to the selected operational mode. The predetermined trip point causes the CBC to appropriately activate and de-activate the on-chip voltage generator to regulate the on-chip generated voltage at the level required by the configured operational mode.

Abstract: A content addressable memory (CAM) device (100) may include a number of sub-blocks (102-8 to 102-15) that can generate CAM search results. In a “search beyond” operation, sub-blocks (102-8 to 102-15) may be excluded from a search operation according to criteria, including a sub-block address and a soft-priority value. A CAM device may include a compare circuit (400) that may compare sub-block address values in a time division multiplexed fashion to establish priority from among multiple CAM sub-blocks.

Abstract: According to one embodiment, a search engine device (100) may include an input (102), search portion (106), and a vote portion (108). A vote portion (108) may receive responses to a search request at inputs. According to precedence information in received responses, a vote portion (108) may generate an output response having its own precedence information.

Abstract: A content addressable memory (CAM) device (100) may include a number of blocks (102-[n?1, n, n+1]) that each generate CAM search results and result compare circuits (104-[n?1, n, n+1] that receive CAM search results from multiple blocks (102-[n?1, n, n?1]), and compare at least a portion of such CAM search results. According to such a comparison result, a compare circuit (104-[n?1, n, n+1]) can generate an output CAM search result for subsequent comparison with CAM search result in another compare circuit (104-[n?1, n, n+1]).

Abstract: A new method of detecting a reticle option layer in an integrated circuit device has been achieved. The method may be applied to detect the presence of the threshold voltage implantation reticle option layer by direct die probing or by probing a pin of a package integrated circuit. The current through a first MOS transistor is measured by forcing a test voltage on the drain and the gate. The gate and the drain of the first MOS transistor are connected together while the source is connected to a reference voltage. The first MOS transistor has the standard threshold implantation but not the threshold voltage reticle option. The current through a second MOS transistor is measured by forcing the same test voltage on the drain and the gate. The gate and said drain of the second MOS transistor are connected together while the source is connected to a reference voltage. The second MOS transistor has the standard threshold voltage implantation and the threshold voltage implantation reticle option layer.

Abstract: A circuit for detecting when a derivative signal has reached its operating level during power-up of an integrated circuit includes a reset circuit, a latch circuit and a node monitoring circuit. The reset circuit, latch circuit and node monitoring circuit are all connected at a node. When power-up starts, the reset circuit causes the level at the node to be driven to an initial level corresponding to the level provided by an external power source. In response to this initial level at the node, the latch circuit generates an output signal with a level indicating that the derivative signal has not yet reached its operating level. The node monitoring circuit monitors the level of the derivative signal. When the level of the derivative signal reaches its operating level, the node monitoring circuit causes the level at the node to change so as to cause the latch circuit to generate the output signal with a level that indicates that the derivative signal has reached its operating level.

Abstract: A circuit for a DRAM is described which, when in test mode, notifies a tester when the self-refresh operation of a dynamic random access memory (DRAM) reaches various stages of completion. By signaling the tester when, i.e., ⅛, ¼, ½, etc. of the self-refresh cycle is reached, the amount of time needed for verification of the self-refresh oscillator frequency is reduced correspondingly by a factor of 8, 4, 2 etc. The signaling of a partial test time is achieved by adding self-refresh status logic circuits which decode the high order most significant bits of the refresh address counter. The activation of the third most significant bit signals completion of ⅛th of the self-refresh cycle, the activation of the second most significant bit signals completion of ¼th of the self-refresh cycle, the activation of the most significant bit signals completion of ½ of the self-refresh cycle, and deactivation of the most significant bit signals completion of the self-refresh cycle.

Abstract: A charge pump limits the voltages at nodes internal to the charge pump to reduce the risk of junction breakdown in the charge pump. The charge pump includes a first pump circuit, a second pump circuit, a first clamp and a second clamp. The first clamp limits the voltage level of a well by providing a current path from the well to the output lead when the voltage level of the well reaches a first predetermined limit. The voltage level at a node from which charge is redistributed to the well is limited by the second clamp, which is configured to provide a conductive path from the node to the output lead when the voltage level of the node reaches a second predetermined limit. The pump circuits can each include a logic circuit that is configured, depending on the level of an external supply voltage, to reduce the rate at which the capacitor node is boosted when the external supply voltage is relatively high.

Abstract: A timing scheme for multiple data clock activation with programmable delay for use in accessing a multiple CAS latency memory device. A multi-stage data propagation path is used to propagate a bit being accessed from a memory array of the device to an output line. Timing signals are generated so that in a CAS latency three mode, the timing signal that activates the next to last stage of the propagation path is triggered by an output clock signal that activates the last stage of the propagation path so that pulse from the output clock signal does not overlap with pulses of the timing signal that activates the previous stage. This timing scheme ensures the data lines feeding the last stage are not being restored while the last stage is sensing these data lines. A programmable delay circuit is used to adjust the timing of the output clock signal.

Abstract: A regulator system for an on-chip-generated supply voltage includes a voltage detection circuit, a power-up mode detection circuit, a normal mode detection path, and a power-up detection path. The voltage detection circuit monitors the on-chip-generated supply voltage and generates a signal that indicates the level of this supply voltage. The power-up mode detection circuit detects when the chip is in the power-up mode and generates a path select signal. The path select signal causes the regulator system to select the power-up detection path during the power-up mode and to select the normal detection path when not in the power-up mode. The power-up detection path includes voltage regulation circuitry that does not rely on a reference voltage. In one embodiment, the power-up detection path includes a logic gate coupled to receive the signal from the voltage detector. The logic gate is skewed to have a trip point that corresponds to voltage level slightly greater than that of the external supply voltage.

Abstract: The present invention provides a method and apparatus that accomplishes a high performance, random read/write SDRAM design by synchronizing the read and write operations at the data line sense amplifier. This enables the design to perform random read and write operations without varying cycle time issues or unbalanced margin issues. The data lines are used as bi-directional lines to accomplish high performance reads and writes with minimal additional wiring overhead required. During a read operation, read data is transferred from the memory cells of the device across a series of consecutive pairs of data lines to an input/output port of the memory device. The first pair of data lines is coupled to a data line sense amplifier. The additional pairs of data lines are coupled to additional amplifiers. During a read operation, data is transferred across the consecutive pairs of data lines according to the timing cycles of the respective amplifiers.

Abstract: A mock wordline timing scheme is used in a memory device having a plurality of memory cells arranged in array blocks. The array blocks are further arranged in groups, with each array block being located between a pair of corresponding sense amplifier banks. Each array block has at least one mock wordline, and each sense amplifier bank is shared by the array blocks located on either side of the sense amplifier bank, except the sense amplifier banks located on the ends of the group of array blocks. Each sense amplifier bank has a corresponding sense timing control circuit coupled to receive an enable signal and a timing signal. In response to an address, a row decoder is configured to be selected to drive the addressed word line. In conjunction with the row decoder, the enable and timing signals of the sense amplifier bank adjacent to the array block containing the addressed memory cell are asserted.