Abstract: A regulator system includes first and second voltage sensing circuits coupled to a voltage generator control circuit. The first and second voltage sensing circuits are configured to monitor the voltage generated by the on-chip voltage generator (i.e., the on-chip supply voltage) and detect when the on-chip supply voltage reaches thresholds that are predetermined to define a desired range of the on-chip supply voltage. The voltage generator control circuit receives voltage sense signals from the voltage sense circuits and, in response, asserts or de-asserts a control signal received by the on-chip voltage generator so as to activate or de-activate the on-chip voltage generator to maintain the on-chip supply voltage within the desired range. The voltage generator control circuit introduces hysteresis in the generation of the control signal provided to the on-chip voltage generator.

Abstract: An activation arrangement for reducing worst case localized supply noise for shared circuitry includes a first group of circuit blocks, a second group of circuit blocks, a shared circuit, and a selection circuit. The first and second circuit blocks are arranged symmetrically about the shared circuit. The selection circuit is configured to selectively activate each circuit block in the first group and, concurrently, a circuit block in the second group corresponding to the circuit block of the first group. The selection circuit is configured so that when the circuit block of the first group that is closest to the shared circuit is to be activated, the corresponding circuit block in the second group is the circuit block that is farthest from the shared circuit.

Abstract: A semiconductor memory device with a pair of data lines for reading and writing data signals to and from a matrix of memory cells and an accelerator circuit for accelerating the generation of a data signal on at least one of the data lines is disclosed. Slow signal generation on the data lines is due to the characteristics of NFET pass gates passing high signals, or PFET pass gates passing low signals. In an implementation using NFET pass gates, the accelerator circuit includes a pair of cross-coupled PFET transistors, one of which is activated by the low signal on the opposing data line. The drains of the cross-coupled PFET transistors are coupled to the data lines, such that when the low signal on the opposing data line activates one of the PFETs, it supplies additional current to the data line receiving the high signal, so as to accelerate the generation of the high signal on the data line.

Abstract: The parameters of a digital signal are extracted by the application of autocorrelation and crosscorrelation techniques to effectively measure the frequency and time behavior of a digital signal. The method employs digital autocorrelation and crosscorrelation to determine these parameters. Autocorrelation allows the measurement of signal frequency by measurement of instantaneous signal phase. Crosscorrelation allows measurement of relative phase between two or more signals in two or more channels by measurement of instantaneous phase and by referencing the instantaneous phase to the autocorrelation function. The autocorrelation function and crosscorrelation function preserve relative amplitude and phase. Measurement of relative amplitude and phase allows direction finding calculation for any current class of system that uses amplitude and/or phase to derive angle or arrival.

Abstract: A timing control circuit (10) is disclosed that provides a timing circuit (12) for controlling the operation of an I/O path circuit (14) in a synchronous static random access memory (SRAM). In a read or write operation, the timing circuit (12) sequentially disables bit line equalization circuits (34), enables sense amplifiers (38), disables I/O line equalization circuits (42), and enables secondary sense amplifiers (44). Further, the timing control (12) initiates a reset operation prior to the completion of the read or write operation. The reset operation includes sequentially enabling the bit line equalization circuits (34), disabling the sense amplifiers (38), enabling the I/O line equalization circuits (42), and disabling the secondary sense amplifiers (44). The timing circuit (12) includes first, second and third delay circuits (20, 22, and 24) to allow for minimum split times for bit line pairs (32) and I/O line pairs (40), and minimum secondary sense amplifier (44) sensing times.

Abstract: A synchronous burst SRAM (110) is disclosed that includes a clock circuit (112) having a phase correction subcircuit (134) and a clock routing subcircuit (132). The clock routing subcircuit (132) provides an internal clock signal to at least one clocked circuit. The phase correction subcircuit (134) is a modified phase locked loop that includes a phase comparator (138) that receives an external clock signal and a delayed internal clock signal. In response to the signals, the phase comparator (138) provides a phase error signal to a charge pump (140) which is coupled to a loop filter (142) to provide an error voltage. The error voltage is coupled to a VCO (144) which provides the internal clock signal as an output. The internal clock signal is coupled to the input of the phase comparator (138) by a feedback circuit which generates the delayed internal clock signal for the phase comparator (138).

Abstract: A timing delay modulation scheme for integrated circuits (10) is disclosed. A super voltage is applied to existing bond pads (30) and detected by super voltage detect circuits (34) which generate a number of logic input signals (22) to a logic unit (18). In response, the logic unit (18) provides a number of control signals (24) which are coupled to timing adjust circuits (20). In the preferred embodiment, in response to its respective control signals, each timing adjust circuit (20) pushes-out or pulls-in, a separate internal timing signal (S0-S3) of the integrated circuit. The super voltage detect circuit (34) includes an adjustable effective super voltage level, and is capable of being disabled. Further, the timing adjustment provided by each timing adjust circuit (20) can be altered.

Abstract: A burst mode static random access memory (SRAM) (10) is disclosed that includes an address transition detect signal (ATD) generating circuit (14) that provides either an asynchronous ATD signal (a-ATD) or a synchronous ATD signal (s-ATD) depending upon the logic state of a mode signal (ATM). A rising edge of the a-ATD signal is generated by a change in address. A falling edge is generated after a predetermined time period according an a-ATD circuit (60) within the ATD generating circuit (14). A falling edge of the s-ATD signal is generated by a rising edge of an internal synchronous clock pulse (CLAT). The rising edge of the s-ATD signal is generated when data are sensed on data lines (40) by an end-of-cycle circuit (20). If ATM is high, the a-ATD signal is used for timing on the SRAM (10). If ATM is low, timing is determined according to the s-ATD signal. An ATD control circuit (16) is provided to generate I/O control signals in response to the ATD signal (either s-ATD or a-ATD).

Abstract: A self-timed synchronous clock pulse circuit (100) is disclosed that includes a pulse pull-down circuit (102) pulling a first pulse node (104) to ground upon receiving the rising edge of an external clock. A pulse generator (108) responsive to a high-to-low transition at the first pulse node (104) generates a second clock pulse. A pulse pull-up circuit (110) is responsive to the second edge of the second clock pulse and pulls the first pulse node (104) to the positive power supply. An initialization circuit (112) is provided to prevent a lock-up condition upon power-up by sampling the logic level of the first pulse node (104) on the rising edge of the external clock. The logic value is essentially held throughout the remainder of the clock cycle by gating the value into a second latch during the second portion of an external clock cycle.

Abstract: An MOS DRAM memory device includes an output buffer having an N-channel output transistor that must receive a boosted gate signal to produce a full Vdd output high logic level signal at the output terminal. The N-channel transistor connects between the Vdd supply voltage and the output terminal. The output buffer connects a Vdd supply voltage to the gate of the output transistor for a short period sufficient to raise the gate to the Vdd voltage level and then disconnects the Vdd supply. The buffer then connects a Vdd+ supply voltage to the gate to increase the gate voltage at least one transistor threshold value above the Vdd supply voltage. This provides the Vdd voltage at the output terminal.

Abstract: A method and apparatus for testing the self-refresh operation of a dynamic memory part are provided in which an oscillator (140) is coupled to a self-refresh counter (142). The self-refresh counter (142) causes a refresh row address counter (144) to generate row addresses for self-refresh cycles. The refresh row address counter (144) is coupled to a self-refresh control circuit (148). The self-refresh control circuit (148) is operable to generate a signal indicating completion of a self-refresh cycle. The refresh row address counter (144) is also coupled to a multiplexer (146). The multiplexer (146) outputs row addresses from either the refresh row address counter (144) or those supplied externally for rows to be refreshed.

Abstract: A synchronous memory device is provided in which a timing and control circuit (28) receives timing and control inputs. A row address buffer (38) and row decoders (40 and 42) operate to enable rows in plural memory sections (30, 32, 34, and 36). Column decoders (58, 60, 62, and 64) operate to enable columns in each of the memory sections (respectively, 32, 36, 30 and 34). The column decoders (58, 60, 62, and 64) decode addresses received from counters (respectively 52, 54, 48, and 50), an adder (46), and a latch (56). Counters (48, 50, 52, and 54) and adder (46) generate column addresses for each memory section based on a starting address, thereby allowing for internal operation at less than the external system frequency. An operation mode register (29) stores mode data for controlling certain operations, and a state machine (130) operates to prevent indeterminate operation if invalid mode data is input to the operation mode register (29).

Abstract: Two separate receivers (120,122) receive the input signal (128) and the clock signal (126). During the inactive state of the clock signal, the first receiver produces a low state output (130) and the second receiver produces a high state output (132). Both outputs feed combinational logic (124), which produces two outputs (142,144) both normally low. Upon transition of the clock signal, the output of only one of the receivers changes state to match the logic state of the input signal. The output of the other receiver maintains its logic state. Upon the change in the clock signal, only one of the combinational logic outputs changes state to a logical high state to indicate the state of the one input signal.

Abstract: The described embodiments of the present invention provide a circuit and method for a two level redundancy scheme for a semiconductor memory device. The memory device has one or more data blocks (12) with each data block (12) having an array of memory cells arranged in addressable rows and columns along row lines and column lines. Each array is configured into sub-blocks (14) with each sub-block having a plurality of the memory cells. The first level redundancy scheme includes a few redundant elements for each sub-block for the replacement of defective elements, as is common in many modern semiconductor devices. The second level redundancy scheme includes at least one redundant sub-block of memory cells as part of the main memory for a fully functional memory device or, as an extra level of redundancy for at least one sub-block of memory cells containing defects which are not repairable using the redundant elements.