Patents by Inventor Michael Chern
Michael Chern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11943500Abstract: According to an aspect, an apparatus may include a media streaming device including electronic circuitry configured to receive media content wirelessly from a media content source, and an output cord segment having a first end portion integrally coupled to a structure of the media streaming device, and a second end portion configured to be coupled to a receiving device, where the electronic circuitry is further configured to transmit the received media content through the output cord segment to the receiving device. The apparatus may include a power cord segment having a first end portion configured to be coupled to the media streaming device, and a second end portion configured to be coupled to a power source.Type: GrantFiled: June 24, 2022Date of Patent: March 26, 2024Assignee: Google LLCInventors: Micah Thomas Collins, Michael Jon Sundermeyer, Kristen Beck, Wenson Chern, Philip Lee Ly, Colleen Mischke, Robert Jason Rose
-
Patent number: 7974136Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).Type: GrantFiled: December 22, 2009Date of Patent: July 5, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Geeng-Chuan Michael Chern, Ben Sheen, Jonathan Pabustan, Der-Tsyr Fan, Yaw Wen Hu, Prateep Tuntasood
-
Patent number: 7874869Abstract: A reconfigurable patch panel and a method of reconfiguring a patch panel comprising a support member supporting at least one adapter, where the at least one adapter comprises a plurality of ports for coupling to electric signal bearing cables. A pivot, associated with each of the at least one adapters, couples the at least one adapter to the support member. The at least one adapter selectively rotates about the pivot to a selected position relative to the support member. A retainer, associated with each of the at least one adapters, couples the support member to the at least one adapter and retains the at least one adapter in the selected position.Type: GrantFiled: March 26, 2009Date of Patent: January 25, 2011Assignee: Cisco Technology, Inc.Inventors: Michael Chern, Saeed Seyed, Tung Po Yang
-
Publication number: 20100248535Abstract: A reconfigurable patch panel and a method of reconfiguring a patch panel comprising a support member supporting at least one adapter, where the at least one adapter comprises a plurality of ports for coupling to electric signal bearing cables. A pivot, associated with each of the at least one adapters, couples the at least one adapter to the support member. The at least one adapter selectively rotates about the pivot to a selected position relative to the support member. A retainer, associated with each of the at least one adapters, couples the support member to the at least one adapter and retains the at least one adapter in the selected position.Type: ApplicationFiled: March 26, 2009Publication date: September 30, 2010Applicant: CISCO TECHNOLOGY, INC.Inventors: Michael Chern, Saeed Seved, Tung Po Yang
-
Publication number: 20100157687Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).Type: ApplicationFiled: December 22, 2009Publication date: June 24, 2010Applicant: Silicon Storage Technology, Inc.Inventors: Geeng-Chuan Michael Chern, Ben Sheen, Jonathan Pabustan, Prateep Tuntasood, Der-Tsyr Fan, Yaw Wen Hu
-
Patent number: 7701248Abstract: The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node. Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A demultiplexer has an input, a switched input and two outputs. The output node is connected to the input of the demultiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output.Type: GrantFiled: April 10, 2008Date of Patent: April 20, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Kai Man Yue, Bomy Chen, Geeng Chuan Michael Chern, Tsung-Lu Syu
-
Patent number: 7668013Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).Type: GrantFiled: February 7, 2008Date of Patent: February 23, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Geeng-Chuan Michael Chern, Ben Sheen, Jonathan Pabustan, Prateep Tuntasood, Der-Tsyr Fan, Yaw Wen Hu
-
Publication number: 20090256590Abstract: The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A multiplexer has an input, a switched input and two outputs. The output node is connected to the input of the multiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output.Type: ApplicationFiled: April 10, 2008Publication date: October 15, 2009Inventors: Kai Man Yue, Bomy Chen, Geeng Chuan Michael Chern, Tsung-Lu Syu
-
Publication number: 20090201744Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).Type: ApplicationFiled: February 7, 2008Publication date: August 13, 2009Inventors: Geeng-Chuan Michael Chern, Ben Sheen, Jonathan Pabustan, Prateep Tuntasood, Der-Tsyr Fan, Yaw Wen Hu
-
Patent number: 7566244Abstract: A circuit board assembly includes a circuit board, and a connector supported by the circuit board. The connector is configured to electrically connect with a pluggable transceiver module having a retention post. The circuit board assembly further includes a cage supported by the circuit board. The cage includes a cage body defining (i) a circuit board side which faces the circuit board, (ii) an opposing side which faces away from the circuit board, and (iii) a cavity within which the module substantially resides during module operation. The connector is substantially disposed within the cavity. The cage further includes a tab is configured to engage the retention post of the module when the module substantially resides within the cavity defined by the cage body. The tab resides on the opposing side defined by the cage body. Such an assembly enables installation of the module with its belly side up.Type: GrantFiled: May 10, 2007Date of Patent: July 28, 2009Assignee: Cisco Technology, Inc.Inventors: Toan Nguyen, Gary Myers, Jimmy Leung, Saeed Seyed, Michael Chern
-
Patent number: 7321493Abstract: An improved heatsink attachment assembly includes a first anchor configured to secure to a first location of the circuit board, and a second anchor configured to secure to a second location of the circuit board. Each anchor includes legs having looped end portions configured to contact the circuit board. The heatsink attachment assembly further includes a heatsink clip configured to concurrently (i) fasten to the anchors when the anchors secure to the circuit board, and (ii) hold a heatsink to against a circuit board component of the circuit board. The looped end portions of the legs prevent the legs from completely passing through holes defined in the circuit board. In some situations, the looped end portions define extended coils (e.g., double loops) for a robust interference fit with the circuit board as well as for enhanced strength and stability.Type: GrantFiled: March 14, 2005Date of Patent: January 22, 2008Assignee: Cisco Technology, Inc.Inventors: Hsing-Sheng Liang, George Sya, Hong Huynh, Michael Koken, Michael Chern, Yuan-Cheng Fang
-
Patent number: 7292456Abstract: A control assembly controls removal of a circuit board from a chassis. The control assembly includes a support member configured to fasten to the circuit board, and a handle pivotally attached to the support member. The handle is configured to swing from an opened position to a closed position relative to the support member during installation of the circuit board within the chassis, and from the closed position to the opened position during removal of the circuit board from the chassis. The control assembly further includes a button configured to move between a biased position and a depressed position relative to the support member. The button is further configured to (i) inhibit removal of the circuit board from the chassis when the button is in the biased position, and (ii) enable removal of the circuit board from the chassis when the button is in the depressed position.Type: GrantFiled: November 15, 2005Date of Patent: November 6, 2007Assignee: Cisco Technology, Inc.Inventors: Jimmy Leung, Mandy Lam, Toan Nguyen, Saeed Seyed, Michael Chern
-
Patent number: 7292458Abstract: A circuit board assembly includes a motherboard defining a motherboard plane, and a daughter board defining a daughter board plane which is substantially parallel to the motherboard plane. The motherboard and the daughter board electrically connect to each other through a set of circuit board connectors. The circuit board assembly further includes a set of edge clips. Each edge clip extends outwardly from the daughter board along the daughter board plane and is configured to operate as a mounting platform through which to physically secure the daughter board to the motherboard.Type: GrantFiled: December 1, 2005Date of Patent: November 6, 2007Assignee: Cisco Technology, Inc.Inventors: Michael Chern, Saeed Seyed, Phillip Ting
-
Publication number: 20070109760Abstract: A control assembly controls removal of a circuit board from a chassis. The control assembly includes a support member configured to fasten to the circuit board, and a handle pivotally attached to the support member. The handle is configured to swing from an opened position to a closed position relative to the support member during installation of the circuit board within the chassis, and from the closed position to the opened position during removal of the circuit board from the chassis. The control assembly further includes a button configured to move between a biased position and a depressed position relative to the support member. The button is further configured to (i) inhibit removal of the circuit board from the chassis when the button is in the biased position, and (ii) enable removal of the circuit board from the chassis when the button is in the depressed position.Type: ApplicationFiled: November 15, 2005Publication date: May 17, 2007Inventors: Jimmy Leung, Mandy Lam, Toan Nguyen, Saeed Seyed, Michael Chern
-
Patent number: 7139174Abstract: A circuit board module has a circuit board, a component mounted to the circuit board, and a heat sink assembly. The heat sink assembly includes a base member having a first edge and a second edge. The base member is configured to operate as a thermal conduit between a first location proximate to the component and a second location distal to the component. The heat sink assembly further includes a first rail member coupled to the base member along the first edge of the base member, a second rail member coupled to the base member along the second edge of the base member, and an actuation mechanism coupled to the base member. The actuation mechanism is configured to move portions of the members toward each other when the base member resides at the first location to fasten the base member to the component.Type: GrantFiled: October 29, 2003Date of Patent: November 21, 2006Assignee: Cisco Technology, Inc.Inventors: Toan Nguyen, Michael Chern, Saeed Seyed
-
Patent number: 7064957Abstract: A heat sink attachment mechanism includes a fastener having an associated compressible member. The fastener defines a flange that, as the fastener secures a heat sink to a circuit board component, is configured to contact a circuit board surface associated with the circuit board component. Contact between the flange and the circuit board minimizes the travel of the fastener relative to the circuit board component and limits the stress generated on the circuit board component or on the solder balls of a ball grid array associated with the circuit boards component by the heat sink. Also, as the fastener secures the heat sink to the circuit board component, the fastener compresses the compressible member against the heat sink, thereby causing the compressible member to expand. Expansion of the compressible member allows the compressible member to absorb changes in the stress applied by the fastener to the heat sink and circuit board component over time.Type: GrantFiled: July 8, 2003Date of Patent: June 20, 2006Assignee: Cisco Technology, Inc.Inventors: Hsing-Sheng Liang, Michael Chern, Hong Huynh, Phillip Ting, Saeed Seyed
-
Publication number: 20060114659Abstract: An improved heatsink attachment assembly includes a first anchor configured to secure to a first location of the circuit board, and a second anchor configured to secure to a second location of the circuit board. Each anchor includes legs having looped end portions configured to contact the circuit board. The heatsink attachment assembly further includes a heatsink clip configured to concurrently (i) fasten to the anchors when the anchors secure to the circuit board, and (ii) hold a heatsink to against a circuit board component of the circuit board. The looped end portions of the legs prevent the legs from completely passing through holes defined in the circuit board. In some situations, the looped end portions define extended coils (e.g., double loops) for a robust interference fit with the circuit board as well as for enhanced strength and stability.Type: ApplicationFiled: March 14, 2005Publication date: June 1, 2006Applicant: Cisco Technology, Inc.Inventors: Hsing-Sheng Liang, George Sya, Hong Huynh, Michael Koken, Michael Chern, Yuan-Cheng Fang
-
Patent number: 6856511Abstract: A retainer directly attaches to a circuit board component and to a heat sink and secures the circuit board component to the heat sink. The retainer provides a mechanical attachment between the heat sink and the circuit board component. Such mechanical attachment maintains thermal communication between the heat sink and the circuit board component in the absence of a thermally conductive adhesive between the heat sink and the circuit board component for the operational life of the circuit board component. Furthermore, because the retainer attaches directly to the circuit board component and to the heat sink, the retainer minimizes the necessity for use of mounting holes in the circuit board associated with the circuit board component to secure the heat sink to the circuit board component.Type: GrantFiled: July 17, 2003Date of Patent: February 15, 2005Assignee: Cisco Technology, Inc.Inventors: Rainier Viernes, Michael Chern
-
Patent number: 6853556Abstract: A motherboard assembly includes a motherboard, a circuit board, and an ejector assembly. The motherboard has a motherboard connector extending from a planar surface of the motherboard. The circuit board has a circuit board connector extending from a planar surface of the circuit board and coupled to the motherboard connector of the motherboard such that the planar surface of the circuit board orients substantially parallel to the planar surface of the motherboard. The ejector assembly orients between the motherboard and the circuit board. During an ejection procedure, the ejector assembly separates the motherboard connector and the circuit board connector while minimizing bending of either the circuit board or the motherboard. By limiting bending of either the circuit board or the motherboard, the ejector assembly minimizes damage to electrical traces or components carried by either the circuit board or the motherboard during the separation process.Type: GrantFiled: January 12, 2004Date of Patent: February 8, 2005Assignee: Cisco Techonology, Inc.Inventors: Gary Lynn Myers, Jack Brown Rector, III, Michael Chern
-
Patent number: D549089Type: GrantFiled: February 21, 2006Date of Patent: August 21, 2007Assignee: Cisco Technology, Inc.Inventors: Frank Jun, Michael Chern, Saeed Seyed