Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in trenches using a first layer of conducting material at the bottom of the trenches, and a second layer of conducting material along sidewalls of the trenches. An etch process is used to etch away portions of the first and second layers of the conductive material to form floating gate blocks of the conductive material having sloping portions that terminate in pointed edges formed along the trench sidewalls. The sharpness of the pointed edges are enhanced by the presence of the conductive material disposed along the trench sidewalls.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in trenches using a first layer of conducting material at the bottom of the trenches, and a second layer of conducting material along sidewalls of the trenches. An etch process is used to etch away portions of the first and second layers of the conductive material in to form floating gate blocks of the conductive material having sloping portions that terminate in pointed edges formed along the trench sidewalls. The sharpness of the pointed edges are enhanced by the presence of the conductive material disposed along the trench sidewalls.

Abstract: A power rectifier having low on resistance, fast recovery time and low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i.e., with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common conductive layer. This provides a low Vf path through the channel regions of the MOSFET cells to the contact metallization on the other side of the integrated circuit. A thin gate structure is formed annularly around pedestal regions on the upper surface of the device and a precisely controlled body implant defines the channel region and allows controllable device characteristics, including gate threshold voltage and Vf.

Abstract: A guide device receives and engages a cutout in a distal pin-bearing edge of a printed circuit board for aligning pins with pin sockets. The alignment device includes a web, sized and shaped to be received in a circuit board cutout and a shelf surface for engaging a part of a major surface of the circuit board, to provide for biaxial guidance during board insertion. By positioning guide devices and circuit board cutouts in different locations, for different circuit boards, insertion of circuit boards in an incorrect slot or location is avoided.

Abstract: A power rectifier having low on resistance, mass recovery times and low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i.e., with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common metallization. This provides a low Vf path through the channel regions of the MOSFET cells to the source region on the other side of the integrated circuit. A thin gate structure is formed annularly around the pedestal regions on the upper surface of the device and a precisely controlled body implant defines the channel region and allows controllable device characteristics, including gate threshold voltage and Vf. A parallel Schottky diode is also provided which increases the switching speed of the MOSFET cells.

Abstract: A power rectifier having low on resistance, mass recovery times and low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i.e., with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common metallization. This provides a low Vf path through the channel regions of the MOSFET cells to the source region on the other side of the integrated circuit. A thin gate structure is formed annularly around the pedestal regions on the upper surface of the device and a precisely controlled body implant defines the channel region and allows controllable device characteristics, including gate threshold voltage and Vf. A parallel Schottky diode is also provided which increases the switching speed of the MOSFET cells.

Abstract: A power rectifier having low on resistance, fast recovery times and very low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i.e., with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common metallization. A self aligned body implant and a shallow silicide drain contact region integrated with a metal silicide drain contact define a narrow channel region and allow very high cell density. This provides a low Vf path through the channel regions of the MOSFET cells to the contact on the other side of the integrated circuit. The present invention further provides a method for manufacturing a rectifier device which provides the above desirable device characteristics in a repeatable manner. Also, only two masking steps are required, reducing processing costs.