Patents by Inventor Michael Ching
Michael Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7966337Abstract: A system and method for prioritizing a fetch order of web pages. The method comprises extracting by a web crawler a set of candidate web pages to be crawled. Each web page in the set of candidate web pages is associated with a website in a computer network. A determination is made to determine if a first website score for the website is in a website score database. The first website score is associated with web pages in the set of candidate web pages if the first website score exists in the website score database. The set of candidate web pages is prioritized with respect to an associated website score for each web page in the candidate set of web pages. Content is retrieved from the set of candidate web. Hyperlinks are extracted from the content. The hyperlinks are stored in a memory unit.Type: GrantFiled: June 23, 2008Date of Patent: June 21, 2011Assignee: International Business Machines CorporationInventors: David L. Blackman, Michael Ching, Stephen Dill, Ivan Eduardo Gonzalez, Adam Marcus, Daniel Norin Meredith, Linda Anh Linh Nguyen
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Patent number: 7755968Abstract: An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.Type: GrantFiled: August 7, 2007Date of Patent: July 13, 2010Assignee: Rambus Inc.Inventors: Steven Woo, Michael Ching, Chad A. Bellows, Wayne S. Richardson, Kurt T. Knorpp, Jun Kim
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Publication number: 20090248631Abstract: A method and system for processing complex long running queries with respect to a database in which the database workload is determined in terms of quality of service (QoS) requirements of with respect to short running queries, which can be of a transactional type, in which long running queries are partitioned into a plurality of sub-queries that satisfy the database QoS requirements, are then processed and the results of processing the plurality of sub-queries are aggregated so as to correspond to the processing of the long running query.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Inventors: Alfredo Alba, Nikolaos Anerousis, Michael Ching, Genady Y. Grabarnik, Larisa Shwartz
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Publication number: 20090136676Abstract: An apparatus for coating at least one food item is disclosed. The apparatus includes a reservoir for housing a liquid medium, a dipping assembly operatively coupled to the reservoir wherein the dipping assembly includes a holding mechanism for holding the at least one food item, and mechanical means operatively coupled to the holding mechanism for moving the holding mechanism into the reservoir whereby the at least one food item is immersed in the liquid medium such that the at least one food item is partially coated with the liquid medium in a predetermined fashion.Type: ApplicationFiled: August 14, 2008Publication date: May 28, 2009Inventor: Michael Ching
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Publication number: 20090119291Abstract: A system and method of crawling at least one website comprising at least one URL includes maintaining a lookup structure comprising all of the URLs known to be on a website; calculating a hub score for each webpage of the website to be recrawled, wherein the hub score measures how likely the to be recrawled webpage includes links to fresh content published on the website; sorting all the to be recrawled pages by their hub scores; and crawling the to be recrawled pages in order from highest hub scores to lowest hub scores. The calculating comprises computing a first value equaling a percentage of a number of new relative URLs on the to be recrawled page; computing a second value equaling a percentage of a previous hub score of the to be recrawled page; and computing the hub score as a sum of the first and the second values.Type: ApplicationFiled: January 5, 2009Publication date: May 7, 2009Applicant: International Business Machines CorporationInventors: Srinivasan Balasubramanian, Michael Ching, Piyoosh Jalan, Satish C. Penmetsa, Andrew S. Tomkins
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Patent number: 7496557Abstract: A system and method of crawling at least one website comprising at least one URL includes maintaining a lookup structure comprising all of the URLs known to be on a website; calculating a hub score for each webpage of the website to be recrawled, wherein the hub score measures how likely the to be recrawled webpage includes links to fresh content published on the website; sorting all the to be recrawled pages by their hub scores; and crawling the to be recrawled pages in order from highest hub scores to lowest hub scores. The calculating comprises computing a first value equaling a percentage of a number of new relative URLs on the to be recrawled page; computing a second value equaling a percentage of a previous hub score of the to be recrawled page; and computing the hub score as a sum of the first and the second values.Type: GrantFiled: September 30, 2005Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: Srinivasan Balasubramanian, Michael Ching, Piyoosh Jalan, Satish C. Penmetsa, Andrew S. Tomkins
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Patent number: 7475069Abstract: A system and method for prioritizing a fetch order of web pages. The method comprises extracting by a web crawler a set of candidate web pages to be crawled. Each web page in the set of candidate web pages is associated with a website in a computer network. A determination is made to determine if a first website score for the website is in a website score database. The first website score is associated with web pages in the set of candidate web pages if the first website score exists in the website score database. The set of candidate web pages is prioritized with respect to an associated website score for each web page in the candidate set of web pages. Content is retrieved from the set of candidate web. Hyperlinks are extracted from the content. The hyperlinks are stored in a memory unit.Type: GrantFiled: March 29, 2006Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: David L. Blackman, Michael Ching, Stephen Dill, Ivan Eduardo Gonzalez, Adam Marcus, Daniel Norin Meredith, Linda Anh Linh Nguyen
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Publication number: 20080276020Abstract: Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components.Type: ApplicationFiled: July 22, 2008Publication date: November 6, 2008Applicant: RAMBUS INC.Inventors: Michael Ching, Steven Woo
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Publication number: 20080256046Abstract: A system and method for prioritizing a fetch order of web pages. The method comprises extracting by a web crawler a set of candidate web pages to be crawled. Each web page in the set of candidate web pages is associated with a website in a computer network. A determination is made to determine if a first website score for the website is in a website score database. The first website score is associated with web pages in the set of candidate web pages if the first website score exists in the website score database. The set of candidate web pages is prioritized with respect to an associated website score for each web page in the candidate set of web pages. Content is retrieved from the set of candidate web. Hyperlinks are extracted from the content. The hyperlinks are stored in a memory unit.Type: ApplicationFiled: June 23, 2008Publication date: October 16, 2008Inventors: David L. Blackman, Michael Ching, Stephen Dill, Ivan Eduardo Gonzalez, Adam Marcus, Daniel Norin Meredith, Linda Anh Linh Nguyen
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Patent number: 7420990Abstract: Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bidirectional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components.Type: GrantFiled: November 10, 2006Date of Patent: September 2, 2008Assignee: Rambus Inc.Inventors: Michael Ching, Steven Woo
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Publication number: 20070268765Abstract: An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.Type: ApplicationFiled: August 7, 2007Publication date: November 22, 2007Inventors: Steven Woo, Michael Ching, Chad Bellows, Wayne Richardson, Kurt Knorpp, Jun Kim
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Publication number: 20070239701Abstract: A system and method for prioritizing a fetch order of web pages. The method comprises extracting by a web crawler a set of candidate web pages to be crawled. Each web page in the set of candidate web pages is associated with a website in a computer network. A determination is made to determine if a first website score for the website is in a website score database. The first website score is associated with web pages in the set of candidate web pages if the first website score exists in the website score database. The set of candidate web pages is prioritized with respect to an associated website score for each web page in the candidate set of web pages. Content is retrieved from the set of candidate web. Hyperlinks are extracted from the content. The hyperlinks are stored in a memory unit.Type: ApplicationFiled: March 29, 2006Publication date: October 11, 2007Applicant: International Business Machines CorporationInventors: David Blackman, Michael Ching, Stephen Dill, Ivan Gonzalez, Adam Marcus, Daniel Meredith, Linda Nguyen
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Patent number: 7254075Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation.Type: GrantFiled: September 30, 2004Date of Patent: August 7, 2007Assignee: Rambus Inc.Inventors: Steven Woo, Michael Ching, Chad A. Bellows, Wayne S. Richardson, Kurt T. Knorpp, Jun Kim
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Publication number: 20070115043Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: ApplicationFiled: January 22, 2007Publication date: May 24, 2007Applicant: RAMBUS INC.Inventors: Billy Garrett, John Dillon, Michael Ching, William Stonecypher, Andy Chan, Matthew Griffin, Nancy Dillon
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Publication number: 20070078811Abstract: A system and method of crawling at least one website comprising at least one URL includes maintaining a lookup structure comprising all of the URLs known to be on a website; calculating a hub score for each webpage of the website to be recrawled, wherein the hub score measures how likely the to be recrawled webpage includes links to fresh content published on the website; sorting all the to be recrawled pages by their hub scores; and crawling the to be recrawled pages in order from highest hub scores to lowest hub scores. The calculating comprises computing a first value equaling a percentage of a number of new relative URLs on the to be recrawled page; computing a second value equaling a percentage of a previous hub score of the to be recrawled page; and computing the hub score as a sum of the first and the second values.Type: ApplicationFiled: September 30, 2005Publication date: April 5, 2007Applicant: International Business Machines CorporationInventors: Srinivasan Balasubramanian, Michael Ching, Piyoosh Jalan, Satish Penmetsa, Andrew Tomkins
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Publication number: 20070071032Abstract: Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bidirectional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components.Type: ApplicationFiled: November 10, 2006Publication date: March 29, 2007Applicant: RAMBU INC.Inventors: Michael Ching, Steven Woo
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Publication number: 20070039140Abstract: An apparatus for preventing removal of, or tampering with, a construction fitting includes two construction element engaging components and a fastener for connecting the two construction element engaging components to one another. The fastener includes a bolt extending between the two construction element engaging components and a nut for tightening on the bolt rigidly connecting the two engaging components with a gap therebetween. A body portion, for at least partially covering a nut, prevents access thereto by an unfastening tool with the body portion extending from the nut to a position alongside the bolt within the gap. A locking device is able to be moved relative to the body portion between a first position, in which the apparatus is removable from the construction fitting, and a second position in which the apparatus is prevented from being removed from the construction fitting with the locking device extending, in the second position, from the body portion in a direction toward the bolt with the gap.Type: ApplicationFiled: September 2, 2004Publication date: February 22, 2007Inventor: Michael Ching
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Patent number: 7158536Abstract: Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components.Type: GrantFiled: January 28, 2004Date of Patent: January 2, 2007Assignee: Rambus Inc.Inventors: Michael Ching, Steven Woo
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Publication number: 20060067146Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation.Type: ApplicationFiled: September 30, 2004Publication date: March 30, 2006Inventors: Steven Woo, Michael Ching, Chad Bellows, Wayne Richardson, Kurt Knorpp, Jun Kim
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Publication number: 20060022724Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.Type: ApplicationFiled: September 27, 2005Publication date: February 2, 2006Inventors: Jared Zerbe, Michael Ching, Abhijit Abhyankar, Richard Barth, Andy Chan, Paul Davis, William Stonecypher