Abstract: A system (130) forwards a telephone call to a user. The system (130) receives a telephone call from a calling party and compares the name of the calling party to a list of names. If the calling party's name matches a name in the list, the system (130) forwards the telephone call to the user.

Abstract: A method is provided for estimating a number of digital subscriber line nodes (220, 230) required to supply, from a line supply source (200), a geographically distributed network of substantially sequentially numbered twisted pair lines with digital subscriber line service. The method comprises the steps of: storing, in number order, data entries for every twisted pair line of the network, each data entry comprising a pair number and a line length of the respective twisted pair line in relation to the line supply source (200); sorting the entries stored in the database by line length; isolating those sorted entries whose twisted pair lines have a line length greater than a predetermined maximum line length in relation to the line supply source (200); sorting the isolated entries by number; and discriminating, from the sorted isolated entries, the presence of discrete groupings of substantially contiguous entries.

Abstract: A switch includes input ports, output ports, and merged buffers corresponding to the output ports. Each of the input ports receives cells of a data packet from a source. The output ports output the cells in an order in which they were received by the input ports. The merged buffers temporarily store the cells received by the input ports. Each of the merged buffers includes an output buffer, and input buffer, and a controller. The output buffer stores cells for transmission by a corresponding one of the output ports. The input buffer temporarily stores cells for rerouting to at least one different one of the output ports. The controller reroutes the cells stored in the input buffer to output buffers corresponding to the different output ports.

Abstract: Provided herein are methods and systems for providing wide bandwidth using the present twisted pair telephone network. The methods and systems increase the bandwidth of ADSL by statistically sharing the bandwidth of many twisted pair in the neighborhood. An active subscriber would communicate over several twisted pair in the neighborhood, thereby obtaining a dramatic increase in bandwidth.

Abstract: This invention relates to the fast reconfiguration of tree switches. In particular, on-chip parallel control signals are time staggered so that they track the propagation of data or information bits. As a result, it is unnecessary to stop the flow of data bits from the data inputs to the data outputs during the reconfiguration of the tree switch.

Abstract: A distributed switch buffer and method for switch buffer enlargement use standard switch chips as modules that are cascaded in multiples to provide arbitrarily large switch buffers for any number of inputs and outputs. Any type of packet switch chip may be used in any combination. A packet that enters the first switch chip in the cascade automatically gets transferred to other switch chips as part of an integrated buffering scheme. Every input of the switch is connected to all of the switch chips in the first stage of the distributed buffer. The queue of each output of the switch is then expanded by adding more stages of switch chips. All outputs of each switch chip go to the inputs of the same switch chip in the next stage of the distributed buffer so that all of the buffer space of all the cascaded switch chips is available to each input port. The queue may be expanded indefinitely by cascading more chips.

Abstract: A signal switch with merged buffer architecture has multiple input ports connected to a circuit switch matrix which partially sorts the input signals based on output port destination. The circuit switch matrix is connected to multiple merged buffers, each in turn connected to a corresponding output port and feedback. Input signals entering the circuit switch matrix are normally sent to the buffer attached to the destination output port of the input signal, but, if more than one input signal is contending for an output port, all but the first contending input signal are misrouted to merged buffers that are not busy. The location in memory of all of the correctly routed and misrouted input signals in the switch is tracked by a control, which also routes input signals to their output port destinations from the merged buffers, and reroutes misrouted input signals to the correct buffers.

Abstract: A switching matrix routes each received input to a unique output port. Each input specifies an output port as a destination. For each output port, a set of inputs contending for the output port is determined. A control for correctly routing selects an input from each set of contending inputs and routes it to the correct output port of the switching matrix. If no input specifies an output port as a destination, that output port is designated as an available output port. A control for misrouting determines the set of available output ports and the set of inputs that have not been correctly routed by the control for correctly routing. The control for misrouting then misroutes each remaining input to one of the available output ports of the switching matrix. The switching matrix may provide status signals for use by the switch in tracking the location of the correctly routed and misrouted inputs.

Abstract: An apparatus and method for push-out of signals from switch buffers ensures that a high percentage of the highest priority input signals are accepted by the switch by using the switch resources to remove lower priority input signals from the switch buffer in order to accommodate higher priority input signals. Signals of any priority may be pushed out of the switch buffer. The apparatus requires a queue with simultaneous read and write capability and a switch that performs one read operation to N write operations, N being the number of input ports. It pushes signals out of the buffer by performing additional "dummy" read operations to read out signals of the specified priority, and then discards the signals by preventing them from entering the parallel-to-serial shift registers. A preferred embodiment of the invention utilizes an ATM CAM-controlled switch fabric, where the CAM receives the arrival number and priority of each cell in the buffer.

Abstract: An asynchronous transmission mode (ATM) memory array capable of storing one ATM packet of data is an n x m array of memory locations, each memory location capable of storing one bit. The array has n columns, where n is the number of bits in an ATM cell of data, and m rows, where m is the number of cells in an ATM packet. The memory array has a plurality of input lines, one for each of said n columns, which together receive n bits simultaneously. It also has n ground lines, one for each of said n columns in said array, each ground line connected to one memory location in each of said n columns in its row; such that each ground line carries the current of only one bit, thereby reducing the noise transients.

Abstract: An asynchronous transfer mode switch with shared memory under the control of a content addressable memory, receives serially through a plurality of input ports a plurality of cells of digital data packets during a specific time period, each packet having a header. The header of each said cell is processed and temporarily stored. The data bits of each cell are temporarily stored, and transferred in parallel to a random access memory, using available addresses in said random access memory. A header processor assigns an arrival number to each received cell, and extracts the output port destination and priority of each cell from said headers. A content addressable memory stores the arrival number, output destination port and priority of each data cell. A read control provides sequentially, in order of priority, arrival numbers, and destination addresses, to said content addressable memory for determining the order in which cells of data are read from said random access memory.

Abstract: An Asynchronous Transfer Mode (ATM) cell alignment assembly aligns an incoming ATM cell within an internal time slot of an ATM matrix by controllably time-delaying the cell before being switched by the matrix. The alignment assembly includes a 53-byte-wide shift register having a serial input receiving the incoming ATM cell, and fifty-three parallel outputs each coupled to a respective input of a 53.times.8 programmable crosspoint switching array. Each output of the array is coupled to an input of a shift register having eight parallel inputs and a serial output coupled to a respective input of the ATM matrix. The crosspoint switching array establishes only a single selected switching path through the array in accordance with the desired time delay, and is reconfigured upon the arrival of each incoming ATM cell.

Abstract: A broadband space switch matrix includes a parallel combination of individual switch modules each comprising a cascade of pass-transistor selectors, NAND gates, and inverters arranged into a multi-stage tree multiplexing configuration. The switching speed is increased by isolating each switching crosspoint from the stray capacitive loading in the matrix.

Abstract: Electrical circuitry of CMOS inverter circuits in cascade providing a compatible interface between ECL logic levels and CMOS logic levels. The ECL input is applied to the gate of the N-type transistor of the first inverter circuit. A threshold control circuit includes a CMOS inverter circuit with the gate of the N-type transistor connected to a reference voltage and the gate of the P-type transistor connected to its drain is connected to the gate of the P-type transistor of the first inverter circuit. The threshold control circuit adjusts the threshold voltage of the first inverter circuit so as to compensate for changes in current flow through the N-type or P-type transistors, thereby permitting operation over extreme variations in circuit parameters under situations of poor operating tolerances and wide temperature variations.

Abstract: Electrical circuitry of CMOS inverter circuits in cascade providing a compatible interface between ECL logic levels and CMOS logic levels. The MOS transistors of the first inverter circuit of the series are approximately three times larger than the MOS transistors of the same type in subsequent inverter circuits of the series. The ECL input is to the gate of the N-type transistor of the first inverter circuit. A threshold control input is connected to the gate of the P-type transistor of the first inverter circuit. This configuration increases the operating speed of the first inverter circuit and permits controlling the threshold voltage in order to stabilize the output duty cycle.

Abstract: A broadband space switch matrix constructed from a plurality of NAND gates arranged into a set of cascaded stages to form a tree-switch multiplexing configuration. A plurality of input digital signals are applied to input ports coupled to the NAND gates in the first stage. A selected one of the input signals emerges as an output signal from an output port coupled to a single NAND gate in the last stage. Each NAND gate has a select line for receiving control signals. The switching path for the selected input signal is established by placing the sequence of NAND gates defined by the selected switching path in a state of conduction whereby only the selected input signal propagates through the switch. This is effected by forcing to a HIGH state the particular NAND gates in each stage whose outputs are coupled to the same NAND gate in the following stage along with the output of the NAND gate in the current stage which is in the chosen path.

Abstract: In a data communication system, apparatus provides a clock signal having a frequency of twice the frequency of a first clock signal. A time delay circuit delays the first clock signal by a time delay to provide a delayed first clock signal. An exclusive OR circuit is coupled to the first clock signal and the delayed first clock signal. The output of the exclusive OR is a second clock signal having a frequency twice the frequency of the first clock signal.

Abstract: Electrical circuitry for changing the operating voltage conditions of CMOS inverter circuitry so as to shift its threshold voltage in a direction to cause the duty cycle of the output signals to equal the duty cycle of the input signals. An average filtered DC output voltage from the inverter circuitry is used as a control signal to a variable voltage supply which changes the operating voltages, thus shifting the threshold level of the inverter circuitry.

Abstract: Apparatus for digital switching of FM signals includes multiple functional switching circuits, each having an input for receiving an FM signal at a first frequency and each generating first switching transients in response to the FM signal. The apparatus includes a dummy switching circuit corresponding to each functional switching circuit. The dummy switching circuits generate second switching transients in response to the FM signal. The second switching transients are shifted in phase relative to the first switching transients such that a crosstalk signal resulting from the first and second switching transients has a frequency of twice the first frequency. The apparatus further includes filters for attenuating the crosstalk signal. By shifting the frequency of the crosstalk signal to twice the frequency of the FM signal, the crosstalk signal is easily filtered.

Abstract: A broadband space tree-switch matrix establishes a desired switching path by sensitizing only the sequence of logic gates defined by the desired path such that only these sensitized logic gates are operable to undergo switching and thereby permit transmission of only the corresponding input signal. The tree-switch includes a plurality of cascaded stages wherein the first stage consists of dual-input NAND gates each receiving a corresponding input signal at one input and a control signal at another input. The remaining stages include a plurality of switching nodes each having a first NAND gate cascaded to a second NAND gate wherein the second NAND gate has a HIGH steady-state logic signal present at one of its inputs. An appropriate combination of control signals are applied to the NAND gates in the first stage to effect a selected switching path. A second broadband space switch matrix comprises a plurality of NAND gates arranged into a series of cascaded stages to form a tree-switch configuration.